The Complete Guide to PCB Assembly & IC Package Types: From 0201 Passives to 1000-Ball BGAs
PCB assembly is where the digital meets the physical — a few microns of solder paste misalignment, and your $40 BGA becomes a paperweight. Understanding package types, pad geometries, and the physics of solder joint formation isn't optional when you're going from prototype to production.
This guide covers every major IC package type, passive component sizing, soldering process physics, and PCB DFM rules that separate a first-pass-yield board from a rework nightmare.
1. The Two Assembly Worlds: Through-Hole vs. Surface Mount
graph TD
A["PCB Assembly<br/>Technology"] --> B["Through-Hole<br/>(THT)"]
A --> C["Surface Mount<br/>(SMT)"]
A --> D["Mixed Technology<br/>(THT + SMT)"]
B --> B1["Wave Soldering"]
B --> B2["Selective Soldering"]
B --> B3["Hand Soldering"]
C --> C1["Reflow Soldering<br/>(IR / Convection / Vapor Phase)"]
D --> D1["Reflow + Wave"]
D --> D2["Reflow + Selective"]
style C1 fill:#51cf66,color:#fff
style D1 fill:#ffd43b,color:#000
Through-Hole Technology (THT) was the standard from the 1950s through the 1980s. Component leads pass through drilled holes and are soldered on the opposite side. Still used for connectors, high-power components, and anything that needs mechanical strength.
Surface Mount Technology (SMT) dominates modern electronics (>95% of components by count). Components sit on top of copper pads, and solder paste—a mixture of microscopic solder spheres in flux—is reflowed to form the joint.
2. Passive Component Packages: The Numbers on Your BOM
The "0402," "0603," and "0805" you see on your BOM are imperial code dimensions (though the metric system uses the same naming convention — confusingly). The numbers give the package length and width in hundredths of an inch:
Imperial Code · Metric Code · Dimensions (mm) · Dimensions (inch) · Power Rating (Typical) · Hand-Solderable?
008004 · 0201M · 0.25 × 0.125 · 0.010 × 0.005 · — · No (microscope + robot)
01005 · 0402M · 0.4 × 0.2 · 0.016 × 0.008 · ~1/32 W · No
0201 · 0603M · 0.6 × 0.3 · 0.024 × 0.012 · ~1/20 W · Extreme difficulty
0402 · 1005M · 1.0 × 0.5 · 0.039 × 0.020 · ~1/16 W · Very difficult
0603 · 1608M · 1.6 × 0.8 · 0.063 × 0.031 · ~1/10 W · Possible with skill
0805 · 2012M · 2.0 × 1.25 · 0.079 × 0.049 · ~1/8 W · Easy
1206 · 3216M · 3.2 × 1.6 · 0.126 × 0.063 · ~1/4 W · Easy
1210 · 3225M · 3.2 × 2.5 · 0.126 × 0.098 · ~1/3 W · Easy
2010 · 5025M · 5.0 × 2.5 · 0.197 × 0.098 · ~1/2 W · Easy
2512 · 6432M · 6.4 × 3.2 · 0.250 × 0.126 · ~1 W · Easy
The Tombstoning Problem
Small passives (0402 and below) are prone to tombstoning — one end lifts off the pad during reflow, standing the component up like a tombstone. The physics behind it:
During reflow, both ends of the component are in liquid solder simultaneously. If one end melts slightly before the other (due to thermal mass differences or uneven pad geometries), the surface tension of the liquid solder on the melted end exerts a torque:
Where F_{ST} = \gamma \times w_{pad} (surface tension × pad width) and L_{component} is the component length. For an 0402 resistor (L = 1.0 mm), \gamma \approx 0.4 N/m for molten SAC305 solder, and w_{pad} \approx 0.5 mm:
This tiny torque is enough to lift the component because an 0402 resistor weighs only ~0.1 mg. The fix: symmetric pad design, balanced copper pour on both pads, and controlled ramp rates during reflow.
DFM Rule for Passives
Package · Min Pad-to-Pad Spacing · Recommended for Prototyping · Recommended for Production
0201 · 0.15 mm · No · Only with automated optical inspection (AOI)
0402 · 0.20 mm · No — use 0603 · Fine with proper stencil
0603 · 0.30 mm · ✅ Best balance · ✅ Standard
0805+ · 0.40 mm · ✅ Easiest to hand-solder · ✅ Standard
3. IC Package Types: The Complete Taxonomy
3.1 Leaded Packages (Gull-Wing & J-Lead)
These have exposed metal leads extending from the package body, soldered to pads on the PCB surface.
SOP — Small Outline Package
The workhorse of low-pin-count ICs. Available in narrow (150 mil body width) and wide (300 mil) variants:
Variant · Pins · Pitch · Body Width · Typical Use
SOIC-8 (SOP-8) · 8 · 1.27 mm · 3.9 mm · Op-amps, EEPROMs, MOSFET drivers
SOIC-14/16 · 14–16 · 1.27 mm · 3.9 mm · Logic gates, analog switches
SOP-20/24/28 · 20–28 · 1.27 mm · 7.5 mm · Microcontrollers, ADCs
SSOP (Shrink SOP) · 8–56 · 0.65 mm · 5.3 mm · Higher density logic
TSSOP (Thin Shrink SOP) · 8–56 · 0.65 mm or 0.5 mm · 4.4 mm · Modern MCUs, sensors
MSOP (Mini SOP) · 8–10 · 0.5 mm · 3.0 mm · Ultra-compact analog
DFM for SOP: The standard 1.27mm pitch SOIC is trivially hand-solderable and inspectable. Below 0.65mm pitch (SSOP/TSSOP), you need solder paste stencil + reflow. The gull-wing lead shape means the solder fillet is visible from the side — making optical inspection straightforward.
QFP — Quad Flat Package
Leads on all four sides. The standard for microcontrollers from the 1990s through 2010s:
Variant · Pins · Pitch Range
QFP-32/44/64 · 32–64 · 0.8–1.0 mm
LQFP (Low-profile QFP) · 32–176 · 0.4–0.8 mm
TQFP (Thin QFP) · 32–128 · 0.4–0.8 mm
The 0.5mm pitch threshold: At 0.5mm pitch and below, solder bridging between adjacent pins becomes the dominant failure mode. The stencil aperture design becomes critical:
A 10–15% reduction in stencil aperture width relative to the copper pad prevents excess solder paste from squeezing out and bridging during reflow.
3.2 Leadless Packages
These packages have metal pads on the bottom of the package body — no exposed leads. The solder joint is entirely underneath the component, invisible to optical inspection.
QFN — Quad Flat No-Leads
The dominant package for modern ICs from op-amps to 32-bit MCUs. Pads are on the bottom perimeter + often a large center thermal pad:
Variant · Pins · Pitch · Key Consideration
QFN-16/20/24 · 16–24 · 0.5–0.65 mm · Thermal pad soldering
QFN-32/48 · 32–48 · 0.4–0.5 mm · Stencil design critical
DFN (Dual Flat No-lead) · 2–10 · 0.5–0.95 mm · Two-sided only
The Thermal Pad Problem: The exposed center pad (EP) serves both as a ground connection and the primary heat dissipation path. If the solder paste coverage on the EP is too high, the package floats on a cushion of molten solder during reflow — lifting the perimeter pads out of contact. If too low, you get poor thermal performance and a weak ground.
The optimal EP stencil coverage is typically 50–70% of the pad area, applied as a grid of small square apertures (window-pane pattern) rather than one large opening:
For a typical 4×4mm EP on a QFN-32 with 0.5mm pitch, this means a 3×3 or 4×4 array of 0.5–0.7mm square stencil apertures.
BGA — Ball Grid Array
The highest-density package type. Solder balls on the underside of the package form the connections. No leads, no perimeter pads — just a grid of spheres:
Variant · Ball Count · Pitch · Typical Application
BGA-64 to BGA-256 · 64–256 · 0.8–1.27 mm · FPGAs, mid-range processors
FBGA (Fine-pitch BGA) · 100–400 · 0.5–0.8 mm · DDR memory, mobile SoCs
PBGA (Plastic BGA) · 256–676 · 1.0–1.27 mm · Desktop CPUs, GPUs
CBGA (Ceramic BGA) · 256–1156 · 1.0–1.27 mm · High-reliability aerospace
The Physics of BGA Collapse:
BGA solder balls are solid spheres before reflow. During reflow, they melt and collapse under the weight of the package. The final standoff height is determined by the balance of surface tension and gravity:
For SAC305 solder (\gamma \approx 0.4 N/m, \rho \approx 7400 kg/m³) with d_{ball} = 0.5 mm balls:
Wait — that can't be right. Let me think again. The actual standoff is much smaller because the surface tension of many balls acting together creates a much stronger restoring force. In practice, the standoff height is approximately 0.35–0.50× the original ball diameter. For a 0.5mm ball, expect ~0.2mm standoff.
The BGA Inspection Problem: Unlike QFP/SOP where solder joints are visible, BGA joints are hidden under the package. The only non-destructive inspection method is X-ray (2D or CT). This is the single biggest downside of BGA — you can't visually verify your solder joints. This makes stencil design, reflow profile control, and pad design absolutely critical.
3.3 Grid Array Variants
Package · Description · Pitch · Inspection
LGA (Land Grid Array) · Flat pads, no balls — uses socket or direct solder · 0.5–1.27 mm · X-ray only if soldered
PGA (Pin Grid Array) · Through-hole pins in a grid · 2.54 mm · Visual (pins visible)
WLCSP (Wafer-Level CSP) · Die itself is the package, balls directly on silicon · 0.35–0.5 mm · X-ray only
PoP (Package-on-Package) · BGA stacked on BGA (e.g., CPU + DDR) · 0.4–0.5 mm · X-ray for bottom package
4. Solder Paste and Stencil Design
4.1 Solder Paste Composition
Solder paste is ~50% solder alloy spheres and ~50% flux by volume, but ~90% metal by weight. The flux serves three functions:
- Remove oxides from pad and component surfaces (activated at ~150°C)
- Prevent re-oxidation during reflow (forms a protective barrier)
- Control rheology — paste must shear-thin during printing but hold shape after
The metal alloy determines the melting point. SAC305 (Sn96.5/Ag3.0/Cu0.5) is the dominant lead-free alloy:
With a pasty range (solidus-to-liquidus gap) for SAC305 of ~2–3°C — nearly eutectic, which is desirable because the narrow range means all solder solidifies almost simultaneously, reducing stress on joints.
4.2 Stencil Aperture Design
The stencil is a laser-cut stainless steel foil (typically 100–150 μm thick) that controls where solder paste is deposited. The area ratio is the critical parameter:
Where:
- L = aperture length
- W = aperture width
- t = stencil thickness
The 0.66 rule: For reliable paste release, AR must be ≥ 0.66. Below this, paste sticks to the aperture walls instead of transferring to the pad. This is why ultra-fine-pitch packages need thinner stencils:
Pitch · Min Aperture Width · Max Stencil Thickness (AR=0.66)
1.27 mm (SOIC) · 0.55 mm · 0.42 mm — any standard thickness works
0.8 mm (QFP) · 0.35 mm · 0.27 mm — 150 μm fine
0.5 mm (QFN/TQFP) · 0.22 mm · 0.17 mm — 120 μm, pushing limits
0.4 mm (BGA/WLCSP) · 0.17 mm · 0.13 mm — 100 μm, step stencil often needed
For boards mixing 0.5mm pitch QFNs with large power components (which need thicker paste), a step stencil — thicker in some regions, thinner in others — is the solution. This adds ~₹2,000–₹5,000 to stencil cost but pays for itself in first-pass yield.
5. The Reflow Profile: Four Zones That Make or Break Your Board
graph LR
A["Preheat<br/>25→150°C<br/>1-3°C/s"] --> B["Soak<br/>150→180°C<br/>60-120s"]
B --> C["Reflow<br/>180→245°C<br/>2-4°C/s<br/>Peak 235-250°C"]
C --> D["Cooling<br/>245→25°C<br/>2-6°C/s"]
style C fill:#ff6b6b,color:#fff
style A fill:#74c0fc,color:#000
style B fill:#ffd43b,color:#000
style D fill:#51cf66,color:#fff
Zone · Temperature Range · Duration · What Happens · What Goes Wrong
Preheat · 25 → 150°C · 60–120s · Solvent evaporation, gradual warmup · Too fast → paste splatter, component cracking
Soak · 150 → 180°C · 60–120s · Flux activation, oxide removal, thermal equalization · Too short → incomplete flux activation; too long → flux exhaustion
Reflow · 180 → 245°C peak · 45–75s above 217°C · Solder melts, wets pads, forms joints · Too hot → component damage, board delamination; too cold → cold joints
Cooling · Peak → 25°C · 2–6°C/s · Solidification, grain structure formation · Too fast → thermal shock, brittle joints; too slow → excessive intermetallic growth
Time Above Liquidus (TAL)
The most important parameter in the reflow zone:
For SAC305 (T_{liquidus} = 217°C), the TAL should be 45–90 seconds. Below 45s, the intermetallic compound (IMC) layer at the pad-solder interface doesn't form properly — weak joints. Above 90s, the IMC grows too thick and becomes brittle.
The IMC layer (typically Cu₆Sn₅ and Cu₃Sn for copper pads) is actually necessary — it's the metallurgical bond between solder and pad. But it's also brittle. The optimal IMC thickness is 1–3 μm. The growth rate follows parabolic kinetics:
Where Q \approx 50-80 kJ/mol for Cu-Sn intermetallic growth. This is why excessive TAL is so damaging — growth accelerates exponentially with temperature.
6. Mixed-Technology Assembly: When THT Meets SMT
Most real boards have both SMT and THT components. The assembly sequence matters:
Option 1: SMT-first (reflow) → THT (wave/selective)
- SMT components on bottom side must be glued in place before wave soldering
- Bottom-side SMT passives need wave solder-compatible orientation (perpendicular to wave direction)
- Most common for production
Option 2: THT-first → SMT (paste-in-hole reflow)
- THT components must survive reflow temperatures (not all connectors can)
- Used for "pin-in-paste" or "intrusive reflow" where THT components are soldered in the reflow oven
- Eliminates wave soldering step
7. DFM Rules: Your Pre-Layout Checklist
General Rules
- Copper balance: Symmetric copper on inner layers prevents warpage during reflow. For every large copper pour on layer 2, have a matching one on layer N-1.
- Thermal relief: Connect pads to copper pours with thermal relief spokes (typically 0.2–0.3mm wide, 4 spokes) — otherwise the pour acts as a heat sink and the pad won't reach reflow temperature.
- Solder mask sliver: Minimum solder mask web between pads: 0.075mm for standard, 0.05mm for advanced processes.
Package-Specific Rules
Package · Pad Extension (toe) · Pad Extension (heel) · Pad Width · Special Considerations
SOP/SOIC · 0.3–0.5 mm · 0.3–0.5 mm · 0.5–0.6 mm · IPC-7351 compliant footprints
QFP (0.8mm) · 0.5 mm · 0.5 mm · 0.4 mm · Standard
QFP (0.5mm) · 0.3 mm · 0.3 mm · 0.22–0.25 mm · Reduced aperture per Section 4.2
QFN · 0 → flush with body · 0.3–0.5 mm inside · 0.25–0.3 mm · Longer heel extension for inspection
BGA (1.0mm) · — · — · 0.45–0.5 mm diameter · NSMD pads preferred
BGA (0.8mm) · — · — · 0.35–0.4 mm diameter · SMD or NSMD
BGA (0.5mm) · — · — · 0.25 mm diameter · NSMD only, via-in-pad common
0402 · 0 → flush · 0.15 mm · 0.5 mm · —
0603 · 0 → flush · 0.2 mm · 0.8 mm · —
NSMD vs. SMD Pads for BGA
- NSMD (Non-Solder Mask Defined): Copper pad is smaller than the solder mask opening. Solder mask doesn't touch the pad. Produces a larger solderable area and better joint reliability — preferred for BGA.
- SMD (Solder Mask Defined): Solder mask overlaps the copper pad, defining the solderable area. Tighter dimensional control but smaller joint area — used when trace escape routing requires it.
8. Inspection Methods: Finding Faults Before They Find You
Method · Detects · Best For · Cost
Visual / Microscope · Bridging, tombstoning, missing components, misalignment · SOP, QFP, passives ≥0603 · ₹0 (labor only)
AOI (Automated Optical Inspection) · Same as visual, plus solder volume estimation · All visible joints, production line · ₹15L–₹40L (machine)
X-Ray (2D) · BGA bridging, voiding, insufficient solder · BGA, QFN thermal pad · ₹40L–₹1Cr (machine)
X-Ray CT (3D) · Full 3D reconstruction of hidden joints · Critical BGA, PoP, failure analysis · ₹1Cr+ or outsourced
ICT (In-Circuit Test) · Opens, shorts, wrong component values · Production validation · ₹2L–₹10L (fixture)
Flying Probe · Opens, shorts, component values (fixture-less) · Prototype, low-volume · ₹10L–₹25L (machine)
For prototypes, visual inspection + flying probe is the sweet spot — you catch assembly defects and electrical faults without spending ₹40L on AOI.
9. India's PCB Assembly Ecosystem
India's PCB assembly capacity has transformed in the last five years. Key players:
- Bangalore: High-complexity assembly (0.4mm BGA, 0201 passives) for aerospace and defense
- Chennai: Consumer electronics volume manufacturing
- Pune / Mumbai: Mixed-technology industrial and automotive
- Noida / Delhi NCR: Telecom and IoT devices
- Coimbatore: Growing cluster for medium-complexity boards
The sweet spot for Indian assembly is 4–8 layer boards with 0.5mm pitch BGAs and 0402 passives — sophisticated enough to need serious process control, but not at the bleeding edge (0.35mm WLCSP) that requires the very latest equipment.
On FabFlow, you can upload Gerber files, BOM, and pick-and-place (CPL) data to get instant assembly quotes from verified Indian manufacturers — including stencil fabrication, component sourcing, and full turnkey assembly.
References
- IPC-7351B. (2010). Generic Requirements for Surface Mount Design and Land Pattern Standard. IPC International. — The authoritative standard for SMT land pattern design, covering every package type in this guide.
- IPC-A-610H. (2020). Acceptability of Electronic Assemblies. IPC International. — The industry standard for solder joint acceptance criteria, covering all inspection classes.
- Wassink, R. J. K. & Verguld, M. M. F. (1995). Manufacturing Techniques for Surface Mount Assemblies. Electrochemical Publications. — Comprehensive text on solder paste rheology, stencil printing physics, and reflow process optimization.
- Tu, K. N. (2007). Solder Joint Technology: Materials, Properties, and Reliability. Springer. — Covers intermetallic compound formation kinetics, electromigration in solder joints, and BGA reliability physics.
- Lau, J. H. (1995). Ball Grid Array Technology. McGraw-Hill. — The foundational reference for BGA design including the collapse dynamics model and reliability prediction.
- Biocca, P. (2018). Stencil Printing Process Optimization. KIC Thermal Proceedings. — Covers the area ratio rule, stencil aperture design, and the 0.66 threshold for paste release.
- FabFlow. (2026). PCB Assembly Services — Gerber Viewer with Instant Quotes from Indian Manufacturers. [Online]. Available: https://www.fabflow.app