PCB Fabrication & Bare Board Manufacturing: The Complete Engineering Guide — Why 50 Ω Is 2.7 mm of Trace on a Two-Layer Board and 0.16 mm on a Four-Layer One, the IPC-2221 Copper Arithmetic from 1 A at 11.8 mil to 5 A at 109 mil, a 0.30 mm Via Measured at 1.2 mΩ, the 64 µm Every Plated Barrel Stretches Through Reflow, an 18 × 24 in Panel Worked to 70 % Utilisation, ENIG's 0.05 µm of Gold and the Black Pad Underneath, 20/20 µm mSAP Lines Behind a 60 µm Etch Wall, the CPCB's 3 mg/L Copper Limit, and a 2026 Rupee Ledger from ₹150 Prototypes to a USD 14 Billion Domestic Target

PCB fabrication in numbers: FR-4 Tg/Td/CTE and the z-expansion every via survives, 50-ohm stackup widths from 2.7 mm to 0.14 mm, the IPC-2221 current arithmetic, via and trace resistance math, drilling, plating, surface finish selection (HASL vs ENIG vs OSP), HDI microvias, panelisation, DFM capability tables, and a 2026 India cost ledger from ₹150 prototypes to USD 14 bn targets.

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PCB Fabrication & Bare Board Manufacturing: The Complete Engineering Guide

This series has spent more than a year taking machines apart — boilers and bearings, pumps and PLCs, conveyors and cleanrooms, forging presses and vacuum chambers — and every one of those guides quietly assumed that one component had already appeared out of nowhere: the printed circuit board that runs the thing. The CNC controller, the SCADA panel, the VFD, the weight indicator on the crane — each is a board, and no guide so far has asked how a board is actually made. This one does.

The neglect is understandable. A PCB looks like a finished product, a black-and-green wafer that arrives in a courier envelope; in truth it is a stratified manufacturing artifact with more process steps than most machined parts, and every one of those steps leaves fingerprints in the numbers a designer must live with. A trace that is 0.10 mm wide at the top is 0.17 mm wide at its base because etching undercuts copper at roughly the foil thickness per side. A "1 oz" outer layer starts life as 0.5 oz foil plus whatever plating the through-holes need. A via that is 0.30 mm in the drill file measures 1.17 mΩ of barrel resistance; a board that is 1.6 mm thick stretches its plated barrels 64 µm every time it passes through reflow; and a panel that is 18 × 24 inches holds twenty of your boards at 70 % utilisation, or eighteen if you rotate one dimension by 90°. Fabrication is where geometry becomes contract.

What follows, section by section:

1. The Board as a Stratified Machine

1.1 What a bare board physically is

A printed circuit board is a composite sandwich: woven E-glass fabric impregnated with epoxy resin (the prepreg and core), bonded under heat and pressure around layers of copper foil, then drilled, plated, printed and finished. The copper is the only electrically active member; everything else exists to hold the copper in place, insulate it, and survive the thermal violence of assembly. The glass fabric is a real textile — the industry's standard weave styles have catalogue numbers like 1080, 2116 and 7628, and the weave density changes everything from dielectric constant to how cleanly a laser can cut it (§2.4).

The composite is made in a press at roughly 180–200 °C and a few hundred psi, and it emerges with a coefficient of thermal expansion in the z-axis that no designer would accept if it were optional. Standard FR-4 expands about 55 ppm/°C below its glass-transition temperature and about 250 ppm/°C above it; integrated between 50 and 260 °C, a standard-grade laminate grows 4.0 % through its thickness, and a high-Tg laminate still grows 2.4–2.8 % [7]. On a 1.6 mm board that is 64 µm of expansion — 45 µm even on the good stuff.

Every one of those microns is imposed on every plated through-hole. A PTH is a copper cylinder whose ends are soldered to pads that sit on the surface; when the board grows 64 µm thicker in the oven, the barrel must stretch with it or crack at the knee. This is why IPC-6012 requires electrodeposited copper in holes to hold > 248 MPa tensile strength and > 12 % elongation (Class 3A: > 275.8 MPa and > 18 %) [3] — the ductility is not a metallurgical vanity, it is the mechanism by which a via survives its fifth reflow. It is also why the industry spent the 2000s moving from eutectic SnPb reflow (peak ~183 °C) to lead-free reflow at 245–260 °C: the higher peak pushed boards deeper into the high-CTE regime, and the high-Tg laminate ladder in §2 became mandatory rather than optional [6][7].

1.2 The other half of the story: bow and twist

The board is also a mechanical part. It must lie flat enough for a stencil printer and a pick-and-place machine, which is why bow and twist are specified at ≤ 0.75 % for surface-mount boards (≤ 1.5 % for others) [3]. A 100 × 100 mm panel bowing 0.75 % has its corners 0.75 mm out of plane; the paste deposit across a 0.4 mm-pitch BGA survives that, barely. When a stackup is asymmetric — three prepreg plies on top and one below, say — the press squeezes it into a potato chip, and the warpage propagates all the way to assembly failures that nobody traces back to lamination. This is why "use a symmetric stackup" is the first rule of stackup design, before impedance is even mentioned.

1.3 Why this guide, why now

Because the board is the one manufactured product that hardware engineers buy without reading a drawing. A machined bracket comes with tolerances, datum schemes and a material callout; a PCB order often goes out as a zip file and a wish. The goal of this guide is to give the board the same treatment this series gives a pressure vessel: here is what the material does, here is what the process can hold, here is what the tests prove, and here is what it costs.

2. The Materials Ladder

2.1 Tg, Td, T288: the three temperatures that decide everything

Tg (glass transition temperature) is where the resin stops behaving like a rigid glass and starts behaving like a soft plastic. Measured by DSC (IPC-TM-650 2.4.25) or DMA (2.4.24.2), it is not a maximum operating temperature — it is the gate below which the laminate is stiff and dimensionally stable, and above which its z-CTE jumps 4–5×. The design rule the industry converged on: Tg should be at least 25 °C above the maximum sustained operating temperature [6].

Td (decomposition temperature) is where the resin begins to chemically fall apart — defined as 5 % weight loss in TGA (IPC-TM-650 2.4.24.6). For lead-free assembly the floor is Td ≥ 325 °C; the working recommendation is ≥ 340 °C [6].

T288 is the practical one: the time a laminate survives at 288 °C before delaminating, in TMA. Plain mid-grade FR-4 manages about 2 minutes; high-Tg grades manage ≥ 20–30 minutes [7]. If a board will see three reflow passes plus rework, T288 is the number to read, because delamination is cumulative-and-silent: the board passes electrical test, then blisters in the field.

2.2 The ladder, with cost ratios

Representative datasheet values from the current mid-market (verify revisions before you write notes) [7]:

Grade · Tg (DSC) · Td · T288 · z-CTE below/above Tg · Expansion 50–260 °C · Dk/Df @ 1 GHz · Relative cost

Standard FR-4 (e.g., S1141) · 140 °C · 310 °C · ≥ 2 min · 55 / 250 ppm/°C · 4.0 % · 4.5 / 0.020 · 1.00×

Mid-Tg (e.g., S1000H) · 150 °C · 335 °C · ≥ 20 min · — · 3.0 % · 4.4 / 0.016 · 1.15×

High-Tg (e.g., S1000-2) · 170 °C · ≥ 340 °C · ≥ 20 min · 42 / 215 · 2.8 % · 4.4 / 0.016 · 1.30×

High-Tg filled (S1000-2M) · 180 °C · 355 °C · ≥ 30 min · 41 / 208 · 2.4 % · 4.6 / 0.018 · ~1.5×

Halogen-free (S1165H) · 165 °C · 370 °C · > 30 min · 45 / 220 · 3.0 % · 4.3 / 0.014 · 1.30×

Premium (Isola 370HR, IT-180A class) · 180 °C · 340 °C · > 30 min · — · 2.7–2.9 % · — · 1.4–1.5×

The engineer's reading: Tg 140 costs 1.0×, Tg 170 costs 1.3×, and the difference buys a 30 % cut in z-expansion (4.0 % → 2.8 %). For a 1.6 mm board that is 64 µm of barrel stretch reduced to 45 µm — and a 10–18 layer stackup that would delaminate on the cheap grade runs for years on the expensive one. For a two-layer Arduino shield, none of this matters. For anything that will be reworked or lives above 100 °C, it is the cheapest reliability money in electronics.

2.3 The dielectric ladder: Dk and Df is where signals live or die

Dk (relative permittivity) sets impedance and signal velocity; Df (loss tangent) sets attenuation. The tree: standard FR-4 lands around Dk 4.2–4.6 and Df 0.020–0.025 at 1 GHz; mid-loss halogen-free grades reach Df 0.014; low-loss materials (modified epoxies up to PTFE composites like Rogers 4350B at Dk 3.48, Df 0.0037) reach Dk 3.3–3.8 with Df 0.003–0.008 at 10 GHz [6][9].

Where that matters, in numbers:

2.4 Same "FR-4", three different dielectric constants

Because a laminate is glass plus resin, and glass and resin have different electrical properties, the weave style decides the Dk — finer weaves carry more resin, and resin has the lower dielectric constant [8]. One common FR-4 system, from the laminate maker's own table:

Glass style · Resin content · Pressed thickness per ply · Dk @ 1 GHz

106 · 71 % · 0.053 mm · 3.66

1080 · 64 % · 0.081 mm · 3.85

2313 / 3313 · 55 % · 0.105 mm · 4.09

2116 · 52 % · 0.123 mm · 4.17

7628 · 43 % · 0.199 mm · 4.40

Two consequences follow. First, impedance is calculated per stackup, not per material name: a 50 Ω line is 0.12 mm wide over a 1080 ply and 0.35 mm wide over a 7628 ply (§3). Second, glass weave matters to lasers: CO₂ laser drilling works poorly through heavy 7628 weave because the glass scatters the beam, which is why HDI microvia layers use 1080 and 2116 instead [12].

2.5 Copper: the only member that does anything

Copper arrives as foil in standard weights — 0.5 oz (17.5 µm), 1 oz (35 µm), 2 oz (70 µm), 3 oz (105 µm) — in two metallurgies: electrodeposited (ED, the default; rougher surface anchors to resin) and rolled-annealed (RA, smoother, for flex). Within ED, foil "profile" grades exist — standard HTE for coarse lines, RTF (reverse-treated) and VLP (very-low-profile) for fine lines and high-frequency loss control. Peel strength lives around 1 N/mm, and the mechanical spec that matters downstream is ductility, because the foil must survive press, drill and 260 °C without cracking [6][7].

The designer's currency is ohms per square: sheet resistance R_s = \rho / t.

Every trace resistance in §6 is that number times the square count (length ÷ width). It is the most useful constant in low-voltage design, and it explains the entire copper-weight price ladder: doubling copper to 2 oz halves resistance but forces vias to ≥ 0.25 mm, minimum features to ≥ 0.15 mm, and board thickness to ≥ 1.2 mm on most standard processes [14].

3. Stackup and Impedance: The Geometry Contract

3.1 A four-layer board, taken apart

Take the most common impedance-controlled design in the world: a 1.6 mm four-layer board with 1 oz outer copper using a standard 7628 stackup. Its cross-section, from the fab's published stackup, is [8]:

Layer · Material · Thickness

L1 copper · outer foil + plating · 0.035 mm (1 oz class)

L1→L2 dielectric · prepreg 7628 × 1 · 0.2104 mm

L2/L3 carry layers · core (with 0.0152 mm inner foils) · 1.1000 mm

L3→L4 dielectric · prepreg 7628 × 1 · 0.2104 mm

L4 copper · outer foil + plating · 0.035 mm

Total · · ≈ 1.59 mm

The signal layers are L1 and L4; L2 is a solid ground plane and L3 a power plane. That order — signal, ground, power, signal — is not aesthetic: every high-speed trace needs a return path directly underneath it, and every plane pair is a built-in decoupling capacitor. It is also why "four layers" is the cheapest EMC upgrade in existence: two extra copper layers for a fraction of a redesign.

3.2 The microstrip equation, worked

The outer-layer trace over a plane is a microstrip, and the industry-standard closed form (IPC-2141A and the Hammerstad–Jensen family; all dimensions in mils) is:

where h is dielectric height to the plane, w trace width and t copper thickness. Solve it for the same 50 Ω target across the stackups we have met:

Stackup · Dielectric below trace · εr · Width for 50 Ω

Two-layer 1.6 mm (h ≈ 1.5 mm) · 1.5 mm FR-4 · 4.5 · ≈ 2.7–2.8 mm (107–109 mil)

Four-layer, 7628 prepreg · 0.210 mm · 4.3–4.4 · ≈ 0.35 mm (13.8 mil)

Four-layer, 2116 prepreg · 0.123 mm · 4.2 · ≈ 0.19 mm

Four-layer, 3313 prepreg · 0.105 mm · 4.1 · ≈ 0.16 mm

Four-layer, 1080 prepreg · 0.081 mm · 3.9 · ≈ 0.12–0.14 mm

Inner-layer stripline, 4L (0.61 mm between planes) · — · 4.3 · ≈ 0.20 mm

Inner-layer stripline, 6L (0.51 mm) · — · 4.2 · ≈ 0.16 mm

Sources: field-solver tables for the field-solved cases [9] and the IPC-2141A closed form for the arithmetic — the two agree to a few percent, which is the point of using published stackups: their Dk values are measured, not nominal [8][9].

Read the table's first row twice: on a two-layer board, 50 Ω is a 2.7 mm-wide trace — wider than most connectors' pin fields — which is why controlled impedance in practice begins at four layers, where the plane can be brought within 0.2 mm of the signal. The whole ladder is one equation's worth of intuition: impedance wants trace width, dielectric height and εr in a fixed relationship, so thin dielectric buys narrow traces (good for escaping fine-pitch parts) at the price of tighter manufacturing tolerance.

3.3 Tolerance: where impedance really goes wrong

Three numbers decide whether your 50 Ω is 50 Ω:

  1. Etch tolerance. Standard processes hold ±20 µm on line width; controlled-impedance lines get ±10 µm or better [9]. Since Z_0 varies roughly as w^{-1/2}, a 10 µm error on a 0.2 mm line is already ~2.5 Ω — 5 % — before the dielectric moved at all [9].
  2. Dielectric height. Z_0 varies roughly as \sqrt{h}: doubling the prepreg thickness raises impedance ~40 % [9]. This is why the fab's standard stackup, not your custom one, is the safe choice — its Dk and ply thicknesses are what the fab measures and compensates for every day.
  3. Measured, not asserted. You cannot probe the impedance of a customer's finished traces, so fabs add impedance coupons — test traces on the panel edge, measured by TDR per IPC-TM-650 2.5.5.7, typically against ±10 % windows (advanced fabs ±5 %) [3][9]. When a fab quotes "controlled impedance", it is quoting the coupon data, not your board.

One more trap for high-speed routing: the same 50 Ω is a different width on every layer and every stackup, and the propagation velocity differs between microstrip and stripline. Length-matching two nets that live on different layers without accounting for the 6.1 vs 7.1 ps/mm split is a classic first-spin failure [9].

3.4 Differential pairs, briefly

USB at 90 Ω and Ethernet at 100 Ω differential are edge-coupled pairs: two microstrips a spacing s apart, with Z_{diff} \approx 2 Z_{odd}. Worked for the common 1.6 mm four-layer with a 0.1 mm prepreg: W = 0.12 mm, S = 0.16 mm hits 90 Ω; on a 7628 stackup the same target needs W/S = 0.39/0.59 mm [9][10]. The design rules that follow — keep the pair coupled at constant spacing, reference one continuous plane under the whole pair, and never route the two halves across a plane split — matter more than the last 5 % of width precision.

4. From Artwork to Bare Board: The Process Line

A four-layer board passes through a sequence of roughly 20 major process steps between copper-clad laminate and packed box. Here is the line, in order, with the numbers each step imposes.

4.1 Inner-layer imaging and etching

Two of the four layers begin as copper-clad cores. Each core is coated with photoresist (a dry film), exposed by a laser direct imager (LDI), developed, and then etched — the unprinted copper is dissolved away. The chemistry of choice for inner layers is cupric chloride (\text{CuCl}_2), a regenerable bath whose depleted Cu⁺ is re-oxidised back to Cu²⁺; the dissolved copper later gets recovered as metal (§9.3). The etch is not anisotropic, and that single fact shapes PCB design:

Etching undercuts the line. A 1 oz (35 µm) line etched from the top down loses roughly one foil thickness per side at the base, so a 0.10 mm feature finishes as a trapezoid ~0.17 mm wide at its base, ~0.135 mm averaged — and a 0.075 mm line becomes 0.145 mm at the base. Fabs compensate artwork for this, which is why "design width = finished width" holds — but it also explains the capability wall: you cannot etch 0.05 mm lines out of 35 µm foil with acceptable geometry. The industry ladder [13]:

Process · Line/space capability

Conventional subtractive print-and-etch · ~60/60 µm

Subtractive + any-layer (thinner outer foil) · ~40/40 µm

Advanced subtractive (thin foil, good imaging) · ~35/35 µm

mSAP (modified semi-additive) · 30/30 → 20/20 µm

SAP (semi-additive, IC-substrate class) · ≤ 10 µm

4.2 Oxide, layup and lamination

Etched inner layers get an oxide treatment (brown/black oxide) so resin can grip copper, then come the ply-fair table: cores and prepreg plies stacked per the drawing, copper foils on the outside, everything aligned to tooling and pressed between steel plates. The press ramps a couple of °C per minute to ≥ 180 °C under a few hundred psi, holds for over an hour so the resin crosslinks, then cools under pressure — releasing hot boards into air is a warpage generator (§1.2).

Registration — how well L1's pads will land on L3's lands — is set here and hardened by drilling: production fabs run mechanical registration budgets around ±75 µm (0.003 in.), tightening to ±25–50 µm with LDI and X-ray targeting, and ±20–25 µm in HDI lines [10][14]. Every annular-ring rule in §8 is that number plus the drill tolerance, wearing a pad.

4.3 Drilling: 150,000 rpm through glass

Multilayer boards are drilled after lamination, through a stack of 1–3 panels, on CNC machines with air-turbine spindles spinning up to 150,000–158,000 rpm — slow by air-turbine standards, because the tool is a tungsten-carbide bit of 0.2–6.5 mm that must clear glass fibers without smearing resin [11]. The worked parameters from a published micro-drill study: 0.25 mm bits at 158,000 rpm, infeed 28 mm/s, retract 300 mm/s, a 0.2 mm aluminium entry sheet on top (it centers the point, reduces burrs) and a 2.6 mm paper-composite backup board below (it stops exit burrs and cools the tip) [11]. Hit rate for mechanical drilling is on the order of 300–600 holes per minute; the bit's life in that same study was 2,000 hits as new, then two repoints for another 1,500–2,000 each — call it ~5,000–6,000 hits per bit, i.e. one 0.25 mm bit drills about twelve 500-hole panels before retirement [11].

Then the geometry wall every designer eventually hits: aspect ratio = board thickness ÷ drill diameter. A 0.2 mm hole in a 1.6 mm board is 8:1, the standard-capability ceiling; 2.0 mm thickness with a 0.25 mm bit is also 8:1. Ask for 12:1 and you leave first-tier capability entirely — "the aperture cannot be compensated," in fab terms [14]. Why the wall exists is a plating story (§4.4), because the depth of that hole is the distance plating current must throw.

After drilling: deburring (the exit burr is copper, and copper burrs break plating), then desmear — a permanganate swell-and-etch that removes the resin smear the drill dragged across the inner-layer copper, and optionally etches back a few microns for maximum barrel-to-land contact.

4.4 Plating: Faraday in a copper sulfate bath

Plated through-holes are made in two stages. First, electroless copper deposits a conductive seed (roughly 0.25–1 µm) on the dielectric walls so that electroplating has something to grow from. Then the board enters the copper sulfate plating line, where ~20–25 µm of copper is grown — IPC-6012 Class 2 requires ≥ 20 µm average in the hole, Class 3 ≥ 25 µm (with 18/20 µm minimum at the thinnest point) [3].

How long does that take? Faraday answers, and the arithmetic is a nice way to feel the fab's schedule:

At the baths' typical current density of 15–20 mA/cm², growing 25 µm takes 57–75 minutes — per plating cycle, with the board's tens of thousands of holes all competing for the same current [3][11]. And current does not distribute evenly: a drilled barrel plates ~50–70 % of the surface thickness at its middle. Work the implication backwards: to guarantee IPC-6012's 25 µm at the barrel center, the surface must see ≈ 38 µm of copper. At 65 % throw, a bath calibrated for a 30 µm surface deposit leaves only ~19.5 µm mid-barrel — a whisker under Class 2's average spec. This single ratio — throw efficiency versus aspect ratio — is why high-aspect vias cost what they cost, and why the common failure mode of a marginal process is not an open via but a thin-mid-barrel via that cracks at thermal cycling, years later [3][11].

On the outer layers, the plated copper stacks on the base foil: what ships as "1 oz" on an outer layer is often 0.5 oz starting foil built up by the plating that the holes need anyway. Inner-layer copper is exactly the foil that was laminated — nothing more.

4.5 Outer imaging, solder mask and legend

After plating, the outer layers are imaged and etched (or tented), then the board gets its coat: liquid photoimageable (LPI) solder mask, printed or curtain-coated, pre-cured, exposed on the LDI, developed, and finally cured near 150 °C for about an hour. The mask is also a design constraint: mask dams between pads have a minimum width — typically 0.10–0.15 mm — below which the dam washes out and the pads bridge at reflow. Green remains the cheapest color because it is the volume product; every other color is a line-cleaning cost.

The legend (silkscreen) is now more often inkjet than screen-printed, which is why modern legends can hold 0.15 mm lines and 0.8–1 mm character heights [14]. Rule of thumb: if a human may ever debug this board, the legend is a feature, not decoration.

4.6 Profiling, and the test ladder

Boards leave the panel by CNC routing (outline tolerance ±0.2 mm) or V-scoring (weaker, ±0.5 mm, only for straight lines) [14]. Inside the outline, every board is electrically tested — flying-probe or bed-of-nails fixture — for opens and shorts against the netlist, 100 % of multilayer boards on serious orders. Around that core sit AOI scans at inner-layer and outer-layer stages, microsections of coupons, solder-float thermal stress (288 °C), ionic cleanliness checks for Class 3 (≤ 1.56 µg/cm² NaCl equivalent) [3], and — if you specified it — TDR impedance coupons (§3.3). The coupon is not a formality: it is the only physical evidence that your 50 Ω met the window.

5. Surface Finishes: The Last 100 Nanometres

The copper that will be soldered must stay solderable between the day it leaves the fab and the day it bakes in the reflow oven — shelf lives from weeks to years, with flatness requirements from "whatever" to sub-micron. The finish choice is therefore a four-way trade among cost, flatness, shelf life and RF loss [10][15]:

Finish · What it deposits · Thickness · Flatness · Shelf life · Fine-pitch / BGA · Relative cost

HASL (lead-free) · SnCu/SAC solder, air-knifed · 1–40 µm (thick, uneven) · ±5–15 µm coplanarity · 12 months · Poor — 0.65 mm pitch floor · 1.0× (cheapest metallic)

ENIG · electroless Ni + immersion Au · Ni 3–6 µm + Au 0.05–0.1 µm (IPC-4552B) · < 0.5 µm · 12 months+ · The default under BGA · 1.8–2.5× (+30–50 % vs HASL on the finish line)

OSP · azole organic film on bare copper · 0.2–0.5 µm · Effectively the copper · 6 months (12 with care) · Excellent · ≈ 1.0–1.2×

Immersion silver · Ag on copper · 0.12–0.4 µm · < 0.5 µm · 6–12 months · Excellent · ≈ 1.5×

Immersion tin · Sn on copper · 0.8–1.2 µm · < 0.5 µm · ~6 months · Good · ≈ 1.3×

ENEPIG · Ni + Pd + Au · Ni 3–6 + Pd 0.05–0.1 + Au 0.03–0.15 µm · < 0.5 µm · 12 months+ · Wire-bond capable · ~1.25× over ENIG

Hard gold · electrolytic Au over Ni · Au 0.5–2 µm · — · 24 months+ · Edge connectors, > 1000 mating cycles · Highest

Three engineering stories hide in that table.

The black pad. ENIG's gold arrives by displacement: gold ions swap with the nickel surface, and the gold bath is therefore always attacking the nickel it is plating onto. Runnable correctly — the default, 3–6 µm Ni under 0.05–0.1 µm Au — it is the most reliable commercial finish. Run it hot or long, and you get hyper-corrosion of the nickel: a joint that passes AOI, passes X-ray, passes electrical test, and then fractures in the field [15]. This is why IPC-4552B caps the gold at 0.05 µm minimum with a typical band to 0.125 µm — and why "more gold for reliability" is exactly backwards. If a supplier offers you thicker gold, ask for their IPC-4552B corrosion rating first [15].

The nickel penalty. Above roughly 1 GHz, ENIG's nickel stops being invisible. Skin depth in copper at 10 GHz is ~0.65 µm; the gold cap is 0.05–0.1 µm — an order of magnitude thinner than the skin — so RF current drives into the nickel beneath regardless of the gold. With nickel ~4× more resistive than copper and ferromagnetic, exposed microstrip gets measurably lossier. Above ~5 GHz on critical lines, the industry answer is immersion silver or OSP — no nickel at all [15].

The shelf-life trade. OSP is the cheapest flat finish and the most fragile: it survives about two to three thermal excursions before wetting degrades, so double-sided assembly with rework is off the menu, and because the film is an insulator, bed-of-nails ICT struggles to probe unsoldered pads [15]. Conversely, HASL survives everything except fine pitch. The decision tree that falls out: through-hole and ≥ 0.65 mm pitch → HASL; anything with a BGA → ENIG; high-volume boards assembled ≤ 6 months after fab → OSP; RF above 5 GHz → immersion silver (accepting the tarnish and sulphur caveats); wire bonding in the flow → ENEPIG [10][15].

6. Current, Heat and the Copper Budget

6.1 IPC-2221: the arithmetic every trace starts with

The industry's trace-width arithmetic comes from IPC-2221's empirical fit between current, copper area and temperature rise:

with A in mil², I in amperes and ΔT in °C. The k values encode cooling physics: an outer trace sheds heat by convection into air; an inner trace is buried in laminate with no convective path, so it gets half the constant — a 2.6× area penalty for the same current and rise [1][2]. Worked at the standard 10 °C rise on 1 oz copper [1]:

Current · External width · Internal width

1 A · 11.8 mil (0.30 mm) · 30.8 mil (0.78 mm)

2 A · 30.8 mil (0.78 mm) · 80 mil (2.03 mm)

5 A · 109 mil (2.77 mm) · 283 mil (7.19 mm)

Notes the table doesn't contain: allowed ΔT is a design decision — 10 °C is conservative, 20 °C common for power traces (1 A drops to 7.8 mil at ΔT 20); the formula is validated to roughly 35 A, 400 mil and 100 °C rise, beyond which use IPC-2152 charts rather than forum advice [2]; and beyond about 5 A a plain trace becomes impractical — the answer switches to copper pours, multiple stitched layers, or a bus bar [1]. The famous design sin here is using the external column for a current that lives on an inner layer (§6.2 shows what it costs in volts).

6.2 Ohms per square in practice

With R_\square = 0.49 mΩ/sq for 1 oz copper (§2.5):

The point of the square-count discipline is that it catches the real killers early: the 20 mm of 0.2 mm-wide trace feeding a 2 A connector (100 squares = 49 mΩ → 98 mV and 0.2 W in a 4 mm² footprint) is a local hot spot that no current-capacity table flags, because the table asks about width, not about where the amps actually go.

6.3 Vias: barrels as resistors

A plated via is a copper tube. Its resistance is \rho L / (\pi d\, t) with d the barrel diameter and t the plating thickness, so for a 1.6 mm board [3]:

Via · Plating · Barrel resistance

0.30 mm · 20 µm (Class 2) · 1.46 mΩ

0.30 mm · 25 µm (Class 3) · 1.17 mΩ

0.45 mm · 25 µm · 0.78 mΩ

10 × 0.30 mm in parallel · 25 µm · 0.117 mΩ

Read across the first two rows: Class 3 plating is also an electrical upgrade — 20 % lower via resistance, free with the reliability spec. Down the column, one via carrying 2 A dissipates 4.7 mW (nothing), and ten vias stitching a ground pour put the net under 0.12 mΩ — which is why copper pours are stitched generously, not sparingly. The practical guidance that circulates in fab datasheets: keep single-via current under ~1 A, parallel vias beyond that, and wherever a via sits in a solder pad (via-in-pad under a 0.4–0.5 mm BGA), specify the via filled and capped (IPC-4761 Types V–VII) so paste cannot wick down the hole [10][12].

6.4 When to stop computing

The IPC arithmetic prices copper for temperature; it does not price infrastructure. The senior move is knowing the exits: pours (a ground plane carries tens of amps at trivial resistance), multiple layers stitched with via farms, 2 oz+ copper for real power distribution, and bus bars on the board edge for the last mile. If your power tree needs a spreadsheet per net to defend a trace width, the net wants copper area, not more width.

7. HDI and the Fine-Line Frontier

7.1 Microvias: laser, small, and ratio-bound

When 0.4–0.5 mm-pitch BGAs arrive, mechanical drilling's 0.2 mm floor is too coarse and too deep. The answer is microvias: laser-drilled holes of 75–150 µm connecting adjacent layers only, then copper-plated like any via. Two laser families do the work: CO₂ (9.4–10.6 µm wavelength, thermal ablation, min hole ~75 µm, 500–2,000 pulses/s) and UV (355 nm, photo-chemical, min hole 50–75 µm, 5,000–30,000 pulses/s) [12].

The governing constraint is aspect ratio ≤ 1:1 (best practice 0.75:1): a 100 µm microvia may connect no more than ~75–100 µm of dielectric. Beyond that, plating thins at the knee, voids hide in the copper fill, and the failure appears — as always — after the board is in service [12][13]. The full HDI rule set that follows [12][13]:

7.2 The structure ladder (IPC-2226)

HDI boards are classified by build-up structure [13]:

IPC-2226 type · Structure · Laminations · Min L/S · Typical

Type I · 1+N+1, blind microvias · 1 · 100 µm · Entry HDI

Type II · 1+N+1 + buried vias · 1 · 100 µm · Moderate density

Type III · 2+N+2, stacked/staggered · 2 · 75–50 µm · 5G, automotive, 0.3–0.4 mm BGA

Any-layer · All microvia · 4+ · 50–40 µm · Phones, modules

A published case study makes the stakes concrete: a 12-layer 2+8+2 module (5G small-cell class) started at 76 % yield with ±40 µm stacked-via registration, ±15 µm etch error, microvia voiding and 0.35 mm/m warpage. After calibration (laser registration ±25 µm, aspect ratio to 0.75:1, etch compensation to ±8 µm, symmetric stackup) it shipped at 95.8 % yield — a 20-point swing from process engineering on the same design [13]. This is why "HDI capable" and "HDI-qualified" are different claims, and why the coupon and the case study, not the capability table, are what you buy.

7.3 mSAP: escaping the trapezoid

The fine-line problem is topological: subtractive etching makes trapezoids (§4.1), and trapezoids destroy impedance control and packing density. mSAP (modified semi-additive processing) inverts the logic [13]: start with ultra-thin copper (1–5 µm seed), image a resist pattern, plate up the traces (18–30 µm) into the resist openings, strip, then flash-etch the remaining seed. Result: near-rectangular cross-sections, tighter pitch and cleaner impedance — the process that carried smartphone boards from 40 µm features to 30/30, then 25/25 and 20/20 µm, and it is the same physics trend now arriving in IC substrates and 5G modules [13]. It requires direct imaging to hold 7.5 µm registration [13], resist lines down to 15 µm to end up with 25 µm copper lines after flash-etch roll-off of 6–10 µm, and automated optical shaping (AOS) to repair nicks and opens that would scrap the panel [13]. Below mSAP sits SAP proper — seed layers of hundreds of nanometres, features ≤ 10 µm — the regime where a "PCB" and a semiconductor package stop being distinguishable [13].

8. The DFM Contract

8.1 What fabs can actually make

Capability tables from mainstream and premium houses, consolidated — treat as the negotiating surface of your order [14]:

Parameter · Mainstream capability · Advanced / premium

Layers · 1–10+ (2–6 typical) · up to 30+ (Amitron, IC-substrate lines more)

Min mechanical drill · 0.20 mm · 0.15 mm

Aspect ratio (PTH) · ≤ 8:1 · 10:1 medium, 12:1 hard

Min trace/space (outer) · 0.10 mm (4 mil) · 0.075 mm (3 mil)

Min trace/space (inner) · 0.10–0.127 mm · 0.075 mm with coordination

Min annular ring (design) · ≥ 0.13 mm · tighter by class

Hole position tolerance · ±0.075 mm · ±0.05 mm

PTH diameter tolerance · ±0.075–0.08 mm · ±0.05 mm

Outline · ±0.2 mm (routed), ±0.5 mm (V-score) · ±0.1 mm

Thickness tolerance · ±10 % (≥ 1.0 mm) / ±0.1 mm (< 1.0 mm) · tighter by RFQ

Mask dam / silk · 0.10–0.15 mm / 0.15 mm line, 0.8 mm height · finer with inkjet

Trace-to-edge · ≥ 0.3 mm (0.5 mm preferred); ≥ 0.4 mm at V-cut · —

BGA pad / gap · ≥ 0.25 mm / ≥ 0.12 mm · 0.2 mm pads in HDI

8.2 The pad formula and the ring that isn't there

The annular ring is what remains of a pad after registration and drill errors have moved the hole — the copper that keeps an off-center hole connected. IPC-6012's class ladder: Class 2 tolerates 90° breakout on external pads (the hole tangent to the pad edge); Class 3 demands a positive ring everywhere — commonly ≥ 50 µm external, ≥ 25 µm internally, no breakout, with lifted or fractured rings rejected outright [3]. The design formula that keeps you out of trouble:

The engineer's reading: specify Class 3 by its process consequences, not its feelings. Class 3 buys 25 µm plating, no breakout, per-lot coupon microsectioning and full traceability — and it costs roughly 15–30 % more [3]. Boards under a car hood, in a plane, or on a patient: yes. A hobby project: Class 2, and spend the delta on better testing.

8.3 Panelisation: the worked 70 %

Your board is never fabricated alone; it travels as one of many on a working panel. The standard panel is 18 × 24 in. (457 × 610 mm); the usable area is smaller — tooling holes, rails and chemistry margins consume the border, so a multilayer job gets about 16 × 22 in. (406 × 559 mm) [16]. Rails run 12.7 mm; arrays sit spaced ~2.5 mm apart for routing; three 1 mm fiducials (2–3× clearance, ≥ 5 mm from the edge) give the pick-and-place eyes [16].

Worked, for a 100 × 80 mm board on that usable area with 2.5 mm gutters:

Two more boards per panel from reorienting a rectangle — 11 % more output from the same press, drill program and chemistry. Industry guidance calls for ≥ 70 % utilisation, and the cost elasticity is real: a 10 % utilisation improvement cuts per-unit cost 8–12 % [16][17]. This is also why "cost scales with area, not dimension": a 100 × 80 board is priced per cm², and why the fab's panel-size choice interacts with yours more than most designers ever learn.

8.4 The fabrication notes that survive quotation

The notes block is a contract; fabs quote against it and reject against it. The lines that prevent 90 % of disputes:

  1. Material by slash sheet: "IPC-4101/126, Tg ≥ 150 °C (DSC), Td ≥ 340 °C (TGA)" — not "FR-4" [6].
  2. Stackup drawing with dielectric thicknesses and copper weights per layer; symmetric.
  3. Impedance callouts per layer with windows — "L1/L4 microstrip 50 Ω ±10 %, 90 Ω differential ±10 %, per IPC-2141A; coupon required" [9].
  4. Finish to a named standard — "ENIG per IPC-4552B, Ni 3–6 µm, Au 0.05–0.1 µm" [15].
  5. Class and addenda — IPC-6012 Class 2/3, auto or space addendum where applicable [3].
  6. The tolerance block — hole, outline, thickness, warpage, mask clearance (§8.1).

Then read the quote backwards: every line item the fab added (10:1 vias, 2 oz, ENIG, impedance, Class 3, 24-hour turn) is a dial you can revisit. Most designs pay for two or three dials they never needed.

9. Quality, Test and the Environment

9.1 Class 2 vs Class 3, in numbers

Requirement · Class 2 · Class 3

Hole-wall copper (avg) · 20 µm · 25 µm

Min thin-area copper · 18 µm · 20 µm

External annular ring · 90° breakout tolerated · No breakout; ≥ ~50 µm ring

Internal ring · 90° breakout tolerated · ≥ 25 µm, no breakout

Plating voids · ≤ 5 %, single/cumulative · ≤ 5 %, single only

Ionic cleanliness · Not required · ≤ 1.56 µg/cm² NaCl equiv.

Bow & twist (SMT) · ≤ 0.75 % · ≤ 0.75 % (stricter control)

Coupon microsection · Sample basis · Per lot, full documentation

Cost impact · Baseline · +15–30 %

That is the whole reliability argument in one table: an extra 5 µm of copper in the barrel, no breakout, and per-lot proof [3]. The invisible columns — traceability, documentation, ionic cleanliness — are what a customer buying for a medical device is actually paying for.

9.2 The test ladder

From the fab's perspective the board is guilty until proven connected: AOI after inner-layer etch and after outer imaging (optical, catches nicks/shorts the etcher made); 100 % electrical test — flying probe or fixture — against the netlist; solder-float thermal stress at 288 °C on coupons; microsection of the same coupons for plating thickness and laminate integrity; TDR impedance coupons for controlled-impedance jobs; and for Class 3, ionic cleanliness and lot documentation [3][14][15]. Above the fab sit the standards that scare people at audits: UL 94V-0 flammability (UL 796), RoHS/REACH substance limits, IATF 16949 discipline for automotive chains, and the Class 3 addenda (automotive, space, military). None of it makes a board good; each of it makes a bad board detectable — which, at volume, is the same thing.

9.3 A PCB shop is a copper refinery that makes boards

The wet processes leave a bill the industry increasingly can't externalise. Inner/outer-layer etch rinse water carries 50–500 mg/L of dissolved copper, swinging batch to batch; plating chelates (EDTA, TEA from bath chemistry) keep copper soluble at pH 10, defeating plain lime precipitation — the single most common reason a PCB effluent plant exceeds India's discharge limit [18]. That limit, from the Environment (Protection) Rules regime that treats electroplating (and by extension board fabs) as a Red Category industry: copper ≤ 3.0 mg/L, nickel ≤ 3.0, total chromium ≤ 2.0, Cr(VI) ≤ 0.1, cyanide ≤ 0.2 [18]. The industry-grade answer is elegant: high-concentration streams (> 50 mg/L) go to electrolytic recovery cells that deposit 99 %+ pure copper cathode, cutting the copper load by 80–95 % at source, and the metal is sold or returned to the etchant supplier [18]. The rest is rinse-water reduction — counterflow rinsing, ion exchange, closed loops — because at ₹/m³ of treatment cost plus brand risk, a fab that recycles its water and its copper isn't being green, it's being solvent.

10. The Ledger

10.1 India's structural gap

The numbers tell the story faster than any policy speech. India's bare-board demand in 2024–25 was USD 4.2 billion, of which USD 3.7 billion (≈ 88 %) was imported; domestic production was only about USD 600 million — but domestic sourcing has been compounding at 27.3 % CAGR over three years, and the projection path runs to roughly USD 14 billion of domestic production by FY 2029–30, about 10 % of the government's USD 150 billion electronics-components target [17]. Global context: a USD 73 billion PCB industry with China holding 50–60 % of capacity and Thailand attracting USD 10 billion+ of new investment — and India's share of the world under 1 % [17]. The report cards converge on one recommendation: 10–12 large plants of ~1 million m²/year capacity each, plus laminate capacity upstream [17].

10.2 The policy plumbing (as of late 2026)

The Electronics Components Manufacturing Scheme (ECMS), notified April 2025 with ₹22,919 crore, had its outlay raised to ₹40,000 crore in the FY 2026–27 budget; as of the latest MeitY releases, 75 applications are approved with expected investment of ₹61,671 crore and 65,040 direct jobs — including the country's first flexible-PCB plant, its first SMD-passive plant, and new copper-clad-laminate (CCL) plants, which matter because laminate is ~30 % of a board's bill of materials [17]. Around it: an anti-dumping duty on Chinese bare boards and CCL (90 % of laminates were imported in 2024, and duty lifted landed laminate costs by USD 1.2–1.5/m², squeezing mid-size fabs below 20 % gross margins [17]), a Department of Telecom mandate that 60 % of the board value in public-sector 5G equipment be sourced locally, rising to 75 % by 2027 (a captive demand pool of ~₹8,000 crore/year at IPC-6012 Class 3 spec [17]), ₹1,200 crore earmarked for PCB R&D under the telecom policy, and marquee projects under construction: AT&S's India base for advanced substrates, Kaynes' 6–8 layer lines, Syrma's ₹1,595 crore Andhra plant, Wipro's ₹500 crore unit, Global HDI's ₹1,500 crore Karnataka line, Tata Electronics' USD 1.6 billion Tamil Nadu campus with an internal rigid-flex line [17].

10.3 What you pay in 2026

Prototypes (5 pc, 100 × 100 mm, 2-layer, 1.6 mm, HASL-class):

Route · Price · Notes

Offshore sticker (via agent, e.g., JLC-class) · ₹150–200 for 5 pc · Before shipping, duty, GST — and before anyone handles customs for you

Offshore all-in via Indian reseller · ₹1,500 for 5 pc (₹2,500 for 4-layer) · GST invoice, duty/customs cleared, 10–12 working days door-to-door [16]

Domestic fab (LionCircuits / PCB Power class) · ₹300–800 for 5 pc, 3–7 days · Domestic tiers reach ₹800–1,500 for premium/express [16]

Metal stencil · ₹1,500–2,500 · The other half of any SMT prototype

Volume (100 × 100 mm, FR4, 1 oz, HASL, standard lead time, tooling amortised) [17]:

Layers · 10 pc · 100 pc · 1,000 pc

2 · USD 4.50–8.00 · USD 1.80–3.00 (≈ ₹160–265) · USD 0.90–1.60 (≈ ₹80–140)

4 · USD 12–20 · USD 4.50–7.00 (≈ ₹400–615) · USD 2.50–4.20

6 · USD 22–36 · USD 8–13 · USD 5.00–8.00

8 · USD 38–60 · USD 14–22 · USD 9–14

The multipliers to memorise: 4 layers ≈ 1.8–2.5× the 2-layer price, 6 layers ≈ 3–4.5×, 8 layers 5–7×, 10+ layers 8–12× at volume [17]. One-time tooling runs USD 25–250 [17]. And the spread that catches every first-time buyer: the same board costs ₹3/cm² as a 5-piece prototype and about ₹2/cm² at 100 pieces with tooling amortised — but under ₹1/cm² at volume. If your project is a product, the prototype premium is the price of being able to be wrong cheaply; if your BOM still shows prototype prices at 1,000 units, someone is routing money to the wrong dial.

10.4 The twelve dials

Every quote is some position on twelve dials: layer count, board area, quantity, min line/space, min drill, aspect ratio > 8:1, copper weight, surface finish, controlled impedance, IPC class, laminate grade, lead time. The senior move is to know which dials your design actually turns. A Bluetooth sensor board needs three of them. A 5G module needs nine. A board that has been quoted "expensive" has almost always paid for a dial nobody needed — 2 oz copper under a signal section, ENIG for aesthetic reasons, an 8:1 via where 6:1 would pass, or 3/3 mil lines on a net that runs at 1 MHz.

Frequently Asked Questions

What trace width do I need for 50 Ω on a four-layer board?

It depends on the stackup, and only on the stackup. Using the fab's standard 1.6 mm four-layer board with a 7628 prepreg (0.21 mm dielectric), the answer is a 0.35 mm (14 mil) trace; switch to a 0.1 mm prepreg and the same 50 Ω is 0.14–0.16 mm; on a two-layer board with a 1.5 mm dielectric it balloons to ~2.7 mm, which is why controlled impedance is practiced on four layers. Compute from Z_0 = \frac{87}{\sqrt{\varepsilon_r+1.41}}\ln\frac{5.98h}{0.8w+t} using the fab's measured Dk for that stackup, hold ±10 %, and order the impedance coupon — the coupon is your only proof.

HASL or ENIG — which surface finish should I specify?

Decide by pitch, storage and frequency, not by habit. HASL is the cheapest metallic finish with the best raw solderability, flat enough down to 0.65 mm pitch, and the right answer for through-hole-heavy, coarse-pitch boards. ENIG (Ni 3–6 µm + Au 0.05–0.1 µm per IPC-4552B) is flat to under half a micron, has a 12-month-plus shelf life, survives multiple reflows, and is the default under any BGA — at 30–50 % more on the finish line. Above ~5 GHz on exposed microstrip ENIG's nickel adds real loss, and immersion silver or OSP wins. And remember the counter-intuitive rule: gold above 0.125 µm is not a premium, it is a corrosion indicator — thick gold means the immersion bath ate the nickel (black pad).

What does an 8:1 aspect ratio mean in practice?

Aspect ratio is board thickness divided by drill diameter, and 8:1 is where mainstream fabs draw the line: a 0.2 mm hole in a 1.6 mm board (8:1) is standard; a 0.25 mm hole through 2.0 mm is also 8:1. The wall exists because plating current cannot throw copper evenly into deep narrow holes — mid-barrel plating runs ~50–70 % of the surface deposit, so guaranteeing IPC-6012's 25 µm in the middle of the barrel requires ~38 µm at the surface. Past 8:1 you are buying process heroics, and past 12:1 most conventional processes can't compensate the drill program at all. If your design needs 10:1, expect to pay for it and to see it in the coupon; if it doesn't, don't.

Why is a 4-layer board cheap to prototype but twice the price at volume?

Because the two regimes price different things. At prototype quantities, the one-time tooling (USD 25–250) dominates, so a 4-layer board's material and lamination extras hide inside a price already carrying setup. At volume, tooling amortises to nothing and the real cost drivers surface: 2× the material, extra lamination cycles, tighter registration, longer drilling programs — landing 4 layers at 1.8–2.5× a 2-layer board, and 6 layers at 3–4.5× [17]. The lesson: prototype pricing tells you very little about your production BOM, and the layer-count decision should be made with both columns in front of you.

Why can't I do controlled impedance on a two-layer board?

You can — but you won't like the trace. With a 1.6 mm board there is no plane within reach, so the dielectric height under an outer trace is ~1.5 mm, and the 50 Ω width for that geometry is 2.7–2.8 mm of trace — wider than BGA pads, wider than most connector pin pitches, and hopeless for routing density. Controlled impedance became practical when four-layer boards brought the reference plane within 0.1–0.2 mm: each halving of dielectric height roughly halves the required width (Z_0 \propto \sqrt{h}). If your design needs 50 Ω lines and two layers, the design needs four layers.

Is it cheaper to import boards from China or buy Indian?

Sticker versus landed, and it depends how much of the supply chain you want to run. Offshore sticker prices are unmatched — ₹150–200 for five 2-layer boards — but you then own freight, customs, duty and GST (or pay an agent ₹1,500 all-in for the same five boards with a GST invoice and zero customs work). Indian fabs run ₹300–800 for the same 5-piece 2-layer prototype with 3–7 day lead times, with no import line at all, and the anti-dumping duty on Chinese bare boards has been narrowing the landed-cost gap on larger orders. The decisive cases are the ones policy designed: telecom/PSU Class 3 boards (60 % local sourcing mandate), anything with a security or supply-chain clause, and volume production where the 27.3 % CAGR of domestic sourcing is your negotiating leverage.

The Discipline in One Page

PCB fabrication is one idea — the board is a manufactured part, and its process history is written into every number you design with — worked through a stack of arithmetic. The laminate sets the thermal contract: standard FR-4 grows 4.0 % through its thickness (64 µm on 1.6 mm), which is the 12 %-elongation copper spec explained, and the Tg ladder (140 → 170 → 180 °C at 1.0 → 1.3 → 1.5× cost) is the cheapest insurance in electronics (§1–2). The stackup sets the geometry contract: 50 Ω is 2.7 mm on two layers and 0.35, 0.19 or 0.15 mm on four, depending on a prepreg ply you chose, with ±10 % windows and a coupon as the only proof (§3). The process line sets the physical limits: etching makes trapezoids, 0.1 mm of 1 oz copper finishes 0.17 mm at the base; drilling runs at 150,000 rpm with ~2,000 hits between repoints; 25 µm of barrel copper is 57–75 minutes of Faraday arithmetic at 50–70 % throw, which is the 8:1 aspect-ratio wall explained; and a 0.30 mm via measures 1.17 mΩ of barrel, 20 % better at Class 3 plating (§4, §6). The finish sets the shelf life: HASL's ±5–15 µm of uneven solder or ENIG's 0.05 µm of gold hiding a hyper-corrosion story, with immersion silver waiting where the nickel would hurt (§5). The front edge — microvias at 1:1, mSAP's rectangular 20/20 µm lines, DI registration at 7.5 µm — is the same physics carried two decimal places further (§7). And the contract is written in capability numbers and a 70 % panel: 0.2 mm drills, 4 mil lines, ±0.075 mm holes, 20-up from an 18 × 24 panel, Class 3's 25 µm and 1.56 µg/cm², and the twelve dials that decide the invoice (§8–10).

The ledger closes the loop. India imports 88 % of its bare boards while building toward USD 14 billion of domestic production by FY30; ECMS has ₹40,000 crore behind it; the prototype you order this week for ₹150, ₹800 or ₹1,500 is the same protocol at three levels of adult supervision (§10). None of this is exotic. It is etch, laminate, drill, plate, mask, finish, test — a 20-step line whose numbers this guide just itemised. Design with them, and the boards stop surprising you.

That is the component every other guide assumed. It has been manufacturable, measurable and missable for seventy years — and the designers who read its process the way this series reads a furnace or a crane will keep shipping boards that work, on the first spin, at the price they quoted.

Previous guides in this series: Industrial Ventilation, Fans & Dust Collection · Lean Manufacturing & Production Systems · Belt Conveyors & Bulk Material Handling · Cranes, Hoists & Rigging · Cleanroom Engineering & Contamination Control · Industrial Refrigeration & Cold Chain Systems · Industrial Electrical Power Distribution · Metrology & Dimensional Inspection · Industrial Furnaces, Kilns & Refractories · Structural Steel Design & Fabrication · Pressure Vessels & Storage Tanks · Process Piping & Pipe Fabrication · Industrial Steam Boilers & Steam Systems · Non-Destructive Testing.

[1] IPC-2221 (Generic Requirements for Printed Board Design), §6.2 conductor spacing/current philosophy and the industry-standard empirical fit I = k\,\Delta T^{0.44} A^{0.725} with k = 0.048 external / 0.024 internal (as implemented in engineering calculators and TI power-design literature such as tidua53; worked widths validated against multiple calculators: 1 A → 11.8 mil external, 30.8 mil internal, 5 A → 109 mil external at ΔT = 10 °C, 1 oz). [2] IPC-2152 (Standard for Determining Current-Carrying Capacity in Printed Board Design) — refined charts accounting for board thickness, planes, and thermal environment; use beyond the IPC-2221 fit's validated range (~35 A, 400 mil, 100 °C rise). [3] IPC-6012E (Qualification and Performance Specification for Rigid Printed Boards) — hole-wall copper Class 2 ≥ 20 µm avg / 18 µm min, Class 3 ≥ 25 µm avg / 20 µm min; surface copper equivalently; annular ring/breakout rules (Class 2 external 90° breakout accepted; Class 3 no breakout, ~50 µm external / 25 µm internal minimum rings); plating voids; ionic cleanliness Class 3 ≤ 1.56 µg/cm² NaCl equivalent; bow & twist ≤ 0.75 % SMT; coupon testing per lot Class 3; electrodeposited copper tensile > 248 MPa / elongation > 12 % (Class 3A > 275.8 MPa / > 18 %); applied tolerances per IPC-6012D/DS comparison tables and Class 3 guides. [4] IPC-A-600 (Acceptability of Printed Boards) — visual acceptance criteria keyed to the performance classes. [5] IPC-TM-650 test methods: 2.4.25 (DSC Tg), 2.4.24.2 (DMA Tg), 2.4.24.6 (TGA Td, 5 % weight loss), 2.4.24.1 (TMA T260/T288/T300 delamination times), 2.4.41 (CTE), 2.4.13.1 (thermal stress, 288 °C solder float), 2.5.5.9 (Dk/Df), 2.5.5.7 (characteristic impedance by TDR), 2.6.7.2 (thermal shock/continuity), 2.6.2.1 (water absorption). [6] IPC-4101 (Specification for Base Materials for Rigid and Multilayer Printed Boards) — slash-sheet system (/21, /24, /26, /99, /126, /129 etc.); design guidance Tg ≥ 25 °C above max operating temperature; lead-free minimums Td ≥ 325 °C (recommended ≥ 340 °C); standard FR-4 Dk ~4.2–4.5, Df ~0.020–0.025 at 1 GHz; low-loss materials Dk 3.3–3.8, Df 0.003–0.008 at 10 GHz; material selection decision tree by application. [7] Laminate datasheets and consolidations: Shengyi S1141 (Tg 140 °C DSC, Td 310 °C, T288 ≥ 2 min, z-CTE 55/250 ppm/°C, expansion 4.0 % 50–260 °C, Dk 4.7@1 MHz / 4.5@1 GHz, Df 0.020@1 GHz, CTI 175–249, cost 1.0×), S1000H (150 °C, Td 335 °C, 1.15×), S1000-2 (170 °C, Td ≥ 340 °C, T288 ≥ 20 min, z-CTE 42/215, expansion 2.8 %, 1.3×), S1000-2M (180 °C DSC / 185 DMA, Td 355 °C, expansion 2.4 %, Dk 4.6 / Df 0.018, water absorption 0.08 %), S1165H halogen-free (165 °C, Td 370 °C, z-CTE 45/220, expansion 3.0 %, Dk 4.3 / Df 0.014, 1.30×), Isola 370HR (180 °C, 340 °C, > 30 min, 2.9 %), ITEQ IT-180A (175–180 °C, 340 °C, > 30 min, 2.7 %); cost-ratio table per raypcb/qfpcb compilations. [8] JLCPCB controlled-impedance stackup data — prepreg dielectric constants (7628: 4.4; 3313: 4.1; 1080: 3.91; 2116: 4.16) and the standard 1.6 mm four-layer stackup (0.035 mm Cu / 0.2104 mm 7628 / 1.1 mm core / 0.2104 mm 7628 / 0.035 mm Cu); glass-style table with resin content, pressed ply thickness and Dk (106: 71 %/0.053 mm/3.66; 1080: 64 %/0.081 mm/3.85; 2313-3313: 55 %/0.105 mm/4.09; 2116: 52 %/0.123 mm/4.17; 7628: 43 %/0.199 mm/4.40) per PCBPlanner stackup guide. [9] Microstrip/stripline equations — IPC-2141A and Hammerstad–Jensen closed forms, Z_0 = (87/\sqrt{\varepsilon_r+1.41})\ln(5.98h/(0.8w+t)); field-solver table (2-layer 1.6 mm ≈ 2.8 mm for 50 Ω; 4-layer thin-prepreg ≈ 0.14–0.16 mm; stripline 4L ≈ 0.20 mm, 6L ≈ 0.16 mm); etch tolerance ±20 µm standard / ±10 µm controlled; 10 µm width error on 0.2 mm ≈ 2.5 Ω (5 %); Z_0 \propto \sqrt{h} (\times2 height ≈ +40 % impedance); t_pd 6.1 ps/mm microstrip vs 7.1 ps/mm stripline on FR-4; FR-4 loss ≈ 0.5–1 dB/cm @ 5 GHz vs 0.1–0.15 dB/cm low-loss; FR-4 Dk dispersion 4.6@1 MHz → 4.2@5 GHz; Rogers 4350B Dk 3.48 ± 0.05 (1–10 GHz), Df 0.0037; per PCBPlanner, rftools.io calculators and PCB impedance references. [10] HDI and via rules — IPC-2226 (HDI structure types I–VI; microvia definition), laser drilling data (CO₂ 9.4–10.6 µm vs UV 355 nm; min hole 75 µm CO₂ / 50–75 µm UV; pulse counts, glass-weave preference for 1080/2116), microvia aspect ratio ≤ 1:1 (0.75:1 preferred), capture pad ≈ via + 100 µm (250 µm for 100 µm via), dielectric 50–100 µm, UV registration ±20 µm, stacked (copper-filled, planarized; max 3-high) vs staggered (offset ≥ 50 µm); via-in-pad filled-and-capped for 0.4–0.5 mm BGA; IPC-4761 via protection Types I–VII (tented through filled-and-capped); summary per JLCPCB laser-drilling guide, hdicircuitboard and pcbcool microvia guides. [11] Drilling and plating process data — WC micro-drill study (0.25 mm drill, 158,000 rpm, infeed 28 mm/s, retract 300 mm/s, 2,000 hits new + repoints, 0.2 mm aluminium entry, 2.6 mm paper backup, hole-registration Cpk vs wear); engineered-entry-material study (125,000 rpm, 100 ipm, true-position-radius vs stack height); air-spindle capability to ~150,000 rpm and deburring practice (Camptech); IPC-6012 hole copper targets as in [3]; Faraday plating arithmetic (Q = m/(M/nF), 25 µm Cu ≈ 68 C/cm², 15–20 mA/cm² → 57–75 min) computed in this guide. [12] Laser/HDI capability and rules — as in [10]; also microvia qualification per IPC-TM-650 2.6.7.2 and IPC-9252 D-coupon protocols; yield case study (12-layer 2+8+2: registration ±40 → ±25 µm, warpage 0.35 → 0.18 mm/m, yield 76 → 95.8 %). [13] mSAP/SAP — Orbotech/Electronic Design "mSAP: The New PCB" (30/30 → 25/25 → 20/20 µm; DI to 10 µm lines with 7.5 µm registration; rectangular vs trapezoidal cross-sections; AOS repair); AT&S mSAP technology description; pcb-technologies/GS Swiss/PCD&F (subtractive print-and-etch limits ~60/60 µm conventional, ~40/40 any-layer, ~35/35 advanced; mSAP 25 µm L/S at ≤ 20 µm Cu with 1–5 µm seed, resist lines to 15 µm, flash-etch roll-off 6–10 µm; SAP ≤ 10 µm). [14] Capability tables — PCBWay (min 4 mil lines; drill 0.2–6.5 mm; aspect ≤ 8, 10 medium, 12 hard; hole position ±0.075 mm; outline ±0.2/±0.5 mm), ITIS/PCBGOGO FR-4 capabilities (outer ≥ 3 mil, inner ≥ 4 mil; annular ring ≥ 0.13 mm; finished hole ±0.08 mm; legend 0.15 mm/0.75 mm; track-to-outline ≥ 0.3 mm), Amitron (registration ±0.003 in. class), PCB Train/Newbury (aspect 6:1–8:1 tiers, legend 50 µm inkjet / 150 µm screen). [15] Surface finishes — IPC-4552B (ENIG: electroless Ni 3–6 µm, immersion Au 0.05 µm min / typical ≤ 0.125 µm, corrosion "Product Rating" method; thick gold as hyper-corrosion indicator), IPC-4553A (immersion silver, ~0.12–0.40 µm; not recommended for Class 3), IPC-4555 (OSP, 0.2–0.5 µm), J-STD-003 solderability; black-pad mechanism and RF nickel-loss discussion (skin depth ~0.65 µm at 10 GHz; nickel ~4× resistivity); thickness/cost/flatness comparison tables per pcbsync, skpcb, zbotic, huaxing; ENEPIG (Pd 0.05–0.1 µm) and hard gold (0.5–2 µm, > 1000 mating cycles) data. [16] Panelisation and pricing — standard panels 18 × 24 in. with ~16 × 22 in. usable for multilayer, rails 12.7 mm, ~2.5 mm routing gaps, 1 mm fiducials ×3 at ≥ 5 mm from edge (PCBSync, PCB Runner, Fastturn); ≥ 70 % utilisation guidance and 0.1 in. inter-array spacing with 1 in. multilayer margins (Electronic Design); utilisation lever of 8–12 % per 10 % improvement, tooling USD 25–250, per-board price table and layer multipliers (PCBSync cost guide); India pricing: WHYPCB all-in prototype ₹1,500/5 pc 2-layer (₹2,500 4-layer) incl. GST/customs, stencils ₹1,500–2,500; domestic fab ranges ₹300–800 (Zbotic 2026 comparison: LionCircuits, PCB Power, JLCPCB ~₹150–200 sticker). [17] India market and policy — ELCINA–Feedback Advisory report via Economic Times (bare-PCB demand USD 4.2 bn, imports USD 3.7 bn ≈ 88 %, domestic ~USD 600 M, 27.3 % CAGR, ~USD 14 bn domestic by FY 2029–30, global USD 73 bn with China 50–60 %, Thailand USD 10 bn+ investment, 10–12 plant recommendation); PIB releases on ECMS (notified 8 Apr 2025, ₹22,919 crore, raised to ₹40,000 crore in FY 2026–27 budget; 75 approvals, ₹61,671 crore expected investment, 65,040 direct jobs; first flexible-PCB and SMD-passive plants; laminate = ~30 % of PCB BOM); Mordor Intelligence India PCB report (DoT 60 % → 75 % local sourcing for public 5G boards by 2027; ₹1,200 crore PCB R&D under the telecom policy; ~90 % laminate import dependence; 30 % anti-dumping duty, +USD 1.2–1.5/m² landed cost; project announcements incl. Syrma ₹1,595 crore Andhra, Wipro ₹500 crore, Global HDI ₹1,500 crore, Tata USD 1.6 bn rigid-flex); IMARC (market-size context; definitions vary). [18] Effluents — CPCB/Environment (Protection) Rules 1986 Schedule I electroplating/metal-finishing discharge limits (Cu ≤ 3.0 mg/L, Ni ≤ 3.0, total Cr ≤ 2.0, Cr(VI) ≤ 0.1, cyanide ≤ 0.2, pH 6–9; Red Category classification; CETP inlet standards) and PCB wastewater notes (etch/rinse copper 50–500 mg/L; EDTA/TEA chelation defeating precipitation; electrolytic recovery > 50 mg/L streams → 99 %+ cathode copper, 80–95 % load reduction) per CPCB-standard references and spans.co.in electronics-wastewater guide. [19] UL 94V-0 / UL 796 (flammability of printed wiring boards), RoHS and REACH substance regimes, IATF 16949, and IPC-6012 automotive/space/military addenda as the audit-level requirements above the base class system.

Note on sources: IPC standards are the governing documents for every specification in this guide; where this guide states thicknesses, tolerances or worked numbers, they are the typical values of mainstream 2026 processes or arithmetic performed on publicly documented datasheet and capability values — always re-run them on your fab's current datasheet, standard stackup and quote, because processes, prices and copper markets move. Fabrication is a contract: write your notes to the standard, order the coupon, and let the arithmetic — not the brochure — approve the stackup.

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