SMT Assembly and Reflow Soldering: Stencil Physics, Paste Volume, Thermal Profiles, and Joint Metallurgy

A 0.20 mm aperture in a 0.12 mm foil has an area ratio of 0.714 — barely above the 0.66 floor where paste stops releasing reliably, and that single number explains most of the defects on the line. This guide works the arithmetic: transfer efficiency and the five-ball rule, 0603 and QFN paste volumes (a 3 mm thermal pad at 60% coverage gives a 36 um standoff and therefore voids), SAC305 profiles with a coldest-joint floor of 228 C, Cu6Sn5 growth of sqrt(kt) with Q = 0.74 eV, tombstoning as a 30:1 surface-tension moment balance, head-in-pillow as dynamic warpage under 76-89 um, thermal-pad voiding at 25% costing a third of the pad, and a 150-placement board costed at Rs 376 at quantity 100.

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SMT Assembly and Reflow Soldering: Stencil Physics, Paste Volume, Thermal Profiles, and Joint Metallurgy

A bare board is a mechanical part with copper on it. It becomes an electronic assembly at exactly one moment: when a measured volume of metal powder suspended in flux is printed through a stainless-steel foil, an odd-shaped ceramic or plastic body is dropped into that paste, and the whole thing is heated until the metal melts and wets.

Everything upstream of that moment is tolerance. Everything downstream is inspection. The moment itself is a fluid-structure-thermal problem that most teams never model, which is why the same 0402 resistor that passes on one build fails on the next, and why a quote for "assembly, 150 placements" can differ by 3× between two vendors who both claim IPC-A-610 Class 2.

This guide works the process quantitatively: stencil area ratio and transfer efficiency, paste and solder volume from aperture geometry, the thermal profile as a metallurgical specification rather than a recipe, intermetallic growth kinetics, and the defect mechanisms — tombstoning, head-in-pillow, thermal-pad voiding — that fall out of the physics when the process window is violated.

1. The line, and where the defects actually come from

flowchart LR
    A[Bare PCB<br/>from fabrication] --> B[Solder paste<br/>stencil print]
    B --> C[3D SPI<br/>volume / height / offset]
    C -->|out of limits| B
    C --> D[Pick and place<br/>+/- 40 um]
    D --> E[Reflow<br/>SAC305 peak 245 C]
    E --> F[AOI / X-ray]
    F -->|defect| G[Rework<br/>hot air + flux]
    G --> F
    F --> H[ICT / flying probe<br/>functional test]
    H --> I[Conformal coat<br/>box build]
    classDef print fill:#1e3a5f,stroke:#38bdf8,color:#ffffff
    classDef insp fill:#f9fafb,stroke:#000000,color:#111827
    class B,C print
    class F,H insp

The commonly quoted industry rule of thumb is that 60–70% of solder defects originate at the printing step. It survives because the mechanism is structural: paste volume is the only process input that sets joint geometry, and it is also the only one with no real-time closed-loop control unless you buy SPI and wire it back to the printer. Placement is servo-controlled to ±40 µm. Reflow is controlled to a few degrees. The stencil printer is a squeegee pushing a non-Newtonian paste through holes, and its output varies with blade angle, pressure, speed, separation rate, paste age, room temperature and humidity.

There is a second reason the number sits where it does: printing errors are latent. A 40% low paste volume does not look wrong. It reflows into a joint with a concave, weak fillet that passes AOI and fails thermal cycling 18 months later. A 30% high deposit bridges two fine-pitch leads immediately and gets caught. The defects that survive inspection are disproportionately printing defects.

A 1,000-placement board at 500 DPMO has a ~39% chance of at least one defect per board:

At N = 1{,}000 and 500 DPMO, P = 1 - 0.9995^{1000} = 0.393. At 200 DPMO it is 0.181. This is why first-pass yield collapses on high-count boards even when the per-joint defect rate looks excellent, and why "we run 200 ppm" is a claim about joints, not about boards.

2. Stencil printing: area ratio is the whole game

2.1 The two ratios

Two dimensionless numbers predict whether paste will release from an aperture onto the pad. The aspect ratio compares aperture width to foil thickness:

The area ratio compares the area of the aperture opening to the area of its sidewalls:

For a circular aperture of diameter D, AR = D/(4T). IPC-7525 sets the 0.66 threshold; below it, the adhesive force of paste on the sidewall competes with the force pulling paste onto the pad, and transfer becomes erratic rather than merely low. Worked example — a 0.20 × 1.20 mm aperture in a 0.12 mm foil:

That passes, but only just. Reduce the foil to 0.10 mm and AR rises to 0.857; widen the aperture to 0.24 mm and it rises to 0.833. Both changes increase paste volume, which is why "reduce stencil thickness" is not a universal fix — it rescues fine-pitch release while starving the thermal pad of a QFN on the same board. That conflict is what step stencils exist to resolve: 0.10 mm over the 0.4 mm-pitch QFP, 0.15 mm over the power section, etched or laser-welded as a single foil.

2.2 Paste type, powder size, and the five-ball rule

Solder powder is classified by particle size in IPC J-STD-005. Only 80% of particles must fall inside the nominal band, so two "Type 4" pastes can behave differently.

IPC type · ≥80% between (µm) · Max 10% between (µm) · <0.5% larger than (µm) · Metal content (% wt) · Practical minimum aperture

Type 3 · 25–45 · 45–60 · 60 · ~88.5 · ~230 µm

Type 4 · 20–38 · 38–50 · 50 · ~88.3 · ~190 µm

Type 5 · 15–25 · 25–40 · 40 · ~88.0 · ~125 µm

Type 6 · 5–15 · 15–25 · 25 · ~87.5 · ~75 µm

The five-ball rule sets the practical floor: the smallest aperture dimension should be at least five times the largest particle. For Type 4 with a 38 µm ceiling that is 190 µm; a 0.4 mm-pitch QFP with a 0.20 mm aperture is right at the limit, and 0.3 mm pitch at 0.15 mm aperture requires Type 5.

There is a cost to going finer that has nothing to do with paste price. Finer powder means more oxide surface area per unit mass, faster flux depletion, and a narrower reflow window. Type 5 and Type 6 pastes are also markedly more sensitive to humidity and shelf life. Print a mixed board with Type 4 unless a specific aperture forces Type 5 — and then consider a stepped stencil so only the fine-pitch region sees the thin foil.

The metal loading is worth internalising: ~88% by weight is roughly 50% by volume, because the flux vehicle is far less dense than the SAC alloy. A 0.10 mm³ paste deposit becomes ~0.05 mm³ of solder. Every volume calculation below uses that factor.

2.3 Transfer efficiency

Transfer efficiency (TE) is the fraction of the aperture cavity that actually lands on the pad:

Above AR 0.66, a well-tuned process runs 85–100% TE; below 0.66 it degrades toward 60–80% and the standard deviation widens faster than the mean falls. Experiments with Type 4 and Type 5 powders found AR could be pushed to ~0.58 while still holding >90% TE — a marginal gain that rarely justifies the paste cost. Electroformed nickel foils and nano-coated stainless foils shift the curve slightly by lowering sidewall surface energy; they do not repeal the geometry.

Practically: use TE = 0.9 for design calculations on apertures above AR 0.7, and TE = 0.75 with a wide uncertainty band below 0.66. If a joint is marginal by calculation, it is marginal in production.

2.4 The printer variables that actually move volume

3. From paste volume to joint geometry

The design calculation chain is short and worth running before releasing a stencil:

where \phi_v \approx 0.5 is metal fraction by volume.

0603 chip resistor. Aperture 0.75 × 0.85 mm, foil 0.12 mm, TE 0.92:

A 0603 termination is roughly 0.3 × 0.3 × 0.8 mm; a 0.035 mm³ fillet over two terminations is a proper heel-and-toe fillet with a concave face. Double the foil to 0.15 mm and you get 0.044 mm³ — enough to wick up the termination and, on a part with a 0.8 mm body, enough to risk the solder touching the component body (a Class 3 defect: maximum fillet height must not contact the non-soldered body).

QFN thermal pad. 3.0 × 3.0 mm pad, 60% aperture coverage, 0.12 mm foil:

Spread over the 9 mm² pad, the mean bond-line thickness is 0.324/9.0 = 36\ \mu\text{m}. That is the number that matters for thermal resistance and for standoff: a 36 µm gap is also the outgassing channel through which flux volatiles must escape during reflow, which is exactly why QFN thermal pads void. At 70% coverage the standoff rises to 42 µm and voiding usually improves; at 100% coverage the part floats, tilts, and opens on one side.

BGA. A 0.45 mm sphere is V = \frac{4}{3}\pi(0.225)^3 = 0.0477\ \text{mm}^3. A 0.40 mm pad printed through 0.10 mm foil at 90% TE contributes 0.0113\ \text{mm}^3 of paste, i.e. 0.0057 mm³ of solder — about 12% of the ball volume. This is why BGA joints are dominated by the ball alloy and the paste's job is mostly flux delivery and pad-side IMC formation. It also explains head-in-pillow: with only 12% of the joint volume available as fresh flux-bearing paste, there is very little chemistry to clean an oxidized sphere.

4. Placement: accuracy, capability, and the feeder economy

Modern chip shooters place 01005 (0.4 × 0.2 mm) parts at ±0.04 mm with C_{pk} \geq 1.0; fine-pitch vision centring reaches ±0.03 mm. Those numbers are machine specifications under ideal conditions, and they are not what determines yield. What determines yield is:

5. Reflow: the thermal profile as a metallurgical specification

5.1 The alloy

SAC305 (Sn96.5/Ag3.0/Cu0.5) is the default lead-free alloy: solidus 217 °C, liquidus 220 °C, density ~7.4 g/cm³, CTE 21–23 ppm/K, thermal conductivity 58–61 W/m·K, electrical resistivity 13.2 µΩ·cm. Its 3 K melting range means it has essentially no pasty zone — it goes from solid to liquid almost isothermally, which is good for collapse and bad for tombstoning (Section 7.1).

For comparison, Sn63Pb37 melts at 183 °C with a true eutectic; low-temperature Sn42/Bi58 melts at 138 °C; SAC405 trades 0.5% Ag for better thermal fatigue at a slightly higher cost; Sb/Bi/Ni-modified SAC alloys push thermal-cycling life further at the cost of a higher melting point and a narrower window.

Mixing systems is a real hazard. Bismuth-bearing solder contaminated with lead forms a Sn-Bi-Pb ternary eutectic at ~96 °C, which segregates to grain boundaries and embrittles the joint. Any shop running BiSn low-temperature paste and SnPb rework on the same line needs a controlled contamination limit (commonly ≤0.1 wt% Pb in the BiSn pot or paste) and separate tooling. The same applies to SnPb rework on a SAC joint: the mixed alloy reflows lower, looks fine, and fails fatigue earlier.

5.2 The four zones, in numbers

Zone · Target · Constraint · What it is for

Preheat · 25 → 150 °C at 1–3 °C/s · <3 °C/s · Solvent evolution without splatter; thermal shock limit for MLCCs

Soak · 150–200 °C for 60–120 s · ΔT across board <10 °C · Flux activation, oxide removal, thermal equalisation

Reflow · Peak 235–250 °C, TAL 45–90 s above 217 °C · Coldest joint ≥228 °C; hottest ≤250 °C · Melting, wetting, IMC formation, collapse

Cooling · 2–4 °C/s · ≤4 °C/s; ≥1 °C/s · Grain refinement without thermal stress

Three constraints collide in the reflow zone. The coldest joint on the board must exceed liquidus by enough to wet — Intel's guidance is ≥228 °C for SAC305/405, which is 11 K of superheat. The hottest joint, typically a small passive near the board edge, must stay under the component's J-STD-020 rating, usually 260 °C but sometimes 245 °C for large bodies. And the ΔT between them must stay inside a window narrow enough that both conditions hold simultaneously. On a board with a 40 g aluminium heatsink and 0201 passives, that window can close entirely, and the answer is a slower conveyor with more zones, a pallet, or a selective thermal shield.

TAL is not a free variable. The as-soldered Cu₆Sn₅ scallop layer is 1–3 µm. Extending TAL beyond ~90 s thickens the IMC and dissolves copper from the pad; shortening below ~45 s risks incomplete wetting and cold joints on high-thermal-mass parts. The 45–90 s band with a 50–70 s optimum covers most assemblies.

5.3 Measuring it

A profile is only valid if it was measured on a loaded board with thermocouples attached to actual joints — not taped to the surface, not on a bare laminate. Minimum: one thermocouple on the largest thermal mass, one on a small passive at the board edge, one near the centre, one on the underside. Attach with high-temperature epoxy or aluminium tape over the bead, and keep the wire gauge ≤0.1 mm so the wire does not conduct heat into the joint.

Two profile shapes dominate:

The choice is a diagnostic decision, not a preference: tombstoning says add soak; head-in-pillow and graping say remove soak.

5.4 Atmosphere

Nitrogen is not a cure-all. Oxygen at ≤1,000 ppm measurably improves wetting and reduces solder balling for conventional pastes; low-residue pastes need <100 ppm to show the same benefit. But lower oxygen also increases tombstoning, because faster wetting means the first termination to wet pulls harder before the second melts. Controlled 500–1,000 ppm is the usual compromise; no nitrogen at all is the right answer for a well-formulated modern paste on a board that is not fine-pitch or area-array.

5.5 Double-sided assembly

Second-side reflow runs the first side's joints back through the oven. Two things change: the board's thermal mass is higher (components on the underside absorb heat), and gravity now acts on the first-side joints, which are molten again. Rules:

6. What the joint actually is

A solder joint is not "metal glued to metal." It is a layered structure: copper pad → Cu₃Sn → Cu₆Sn₅ → bulk solder → Cu₆Sn₅ → Cu₃Sn → component termination, with Ag₃Sn plates and Cu₆Sn₅ particles dispersed in the bulk.

The intermetallic layers are necessary — they are the metallurgical bond — and they are brittle. A 1–3 µm total IMC is a good joint. A 10 µm layer is a crack path.

Solid-state IMC growth is diffusion-controlled and parabolic:

For SAC305 on copper, NIST measurements give a total IMC thickness of 13.6 µm after 500 h at 150 °C, with an activation energy of 0.74 eV/atom. That gives k(150\,°C) = 13.6^2/500 = 0.37\ \mu\text{m}^2/\text{h}. Extrapolating the same Arrhenius fit:

Over 10 years (87,600 h), x = \sqrt{7.3\times10^{-5} \times 87600} = 2.5\ \mu\text{m} of additional IMC at room temperature. At 125 °C the rate constant rises by a factor of ~1,400 to 0.10 µm²/h, so 1,000 h of high-temperature storage adds ~10 µm — comparable to the 13.6 µm total reached after 500 h at 150 °C. The lesson is that IMC growth is a service-temperature problem, not a shelf-life problem — and it is why a 125 °C-rated assembly and a 25 °C assembly with identical reflow profiles have different field lives. (Parabolic growth cannot be extrapolated indefinitely; once the layers consume the available copper the joint has already failed by another mechanism.)

Cooling rate sets the bulk microstructure. Fast cooling (2–4 °C/s) refines the Ag₃Sn and Cu₆Sn₅ dispersion and improves fatigue life; very fast cooling (>6 °C/s) can crack the IMC layer through CTE mismatch; slow cooling (<1 °C/s) coarsens Ag₃Sn into large plates, which are crack initiation sites under thermal cycling. The 2–4 °C/s band is not arbitrary — it is the window between segregation and stress.

Thermal fatigue of the joint itself (Coffin–Manson, Engelmaier, the solder-joint fatigue models) is covered in the fatigue and fracture mechanics guide. The relevant summary: solder joints fail by low-cycle fatigue driven by ΔT and dwell time, and the acceleration factor between a 0–100 °C test and a 25–75 °C service condition is far larger than the temperature ratio suggests.

7. The defect physics

Defect · Mechanism · Process lever · Design lever

Tombstoning · Unequal wetting moment on two terminations · Soak profile, slower ramp, more paste · Symmetric pads, balanced copper

Bridging · Excess paste volume, slump, poor separation · Aperture reduction, pressure, paste rheology · Pitch and mask web

Graping · Flux exhausted before coalescence · Shorter soak, lower peak, fresher paste · Smaller thermal mass

Head-in-pillow · Dynamic package warpage separates ball from paste · Shorter soak, lower peak, more paste · Warpage spec, board support

Thermal-pad voiding · Trapped volatiles under low standoff · Aperture segmentation, paste chemistry · Via-in-pad fill, mask-defined channels

Cold joint · Insufficient peak or TAL on high-mass part · Raise peak, extend TAL, slow conveyor · Thermal relief, copper balance

Solder beading · Paste squeezed beside the pad · Placement force, aperture, stencil clean · Mask dam height

Wicking / wicking opens · Thermal imbalance, via-in-pad · Preheating, paste volume · Filled and capped vias

7.1 Tombstoning: the moment balance

A 0603 ceramic body has a volume of ~1 mm³ and a mass of ~5.5 mg, so its weight is ~54 µN. The surface tension of molten SAC305 is ~0.5 N/m; over the wetted perimeter of one termination (~3 mm of contact line) the wetting force is on the order of 1.5 mN — roughly 30× the part's weight. Gravity is irrelevant. Tombstoning is a balance of two surface-tension moments, and it happens when one end wets and pulls before the other end's paste has melted:

With \gamma = 0.5 N/m, P = 3 mm, h = 0.4 mm, M_{\text{wet}} \approx 0.6\ \mu\text{N·m} versus M_{\text{grav}} \approx 0.02\ \mu\text{N·m} — a factor of ~30. And it is the asymmetry between the two ends that decides, not the absolute value.

The causes, in order of frequency: asymmetric copper (one pad tied to a ground plane, the other to a trace), unequal paste volume between the two apertures, a stencil aperture offset that places paste outside the termination, uneven heating across the board (leading edge first), and nitrogen atmosphere accelerating the first wet.

Fixes that work: symmetric pad geometry and copper balancing, a soak profile that equalises temperature before liquidus, aperture design centred on the termination, and paste with a wider melting range or higher tack. Nitrogen off if it is not needed.

7.2 Head-in-pillow and dynamic warpage

Head-in-pillow (HiP) is a BGA/CSP joint where the ball and the paste both melted but never coalesced. The ball sits in a depression in the paste — a head on a pillow. It passes in-circuit test under light probe pressure and fails in the field.

The mechanism is a gap that opens and closes. As the package heats, CTE mismatch between the substrate (~15–17 ppm/K) and the die (~2.6 ppm/K) bows it; the ball lifts off the paste, its surface oxidizes because there is no flux touching it, and the flux in the paste is consumed cleaning the pad. When the package flattens again at peak, the ball re-contacts a paste whose flux is spent. No coalescence.

Measured warpage limits from the literature: dynamic warpage below ~3.5 mils (89 µm) for 0.8 mm pitch and above with a 5–6 mil stencil, and below ~3 mils (76 µm) for finer pitch or thinner stencils. Board warpage is a second contributor: a 0.6 mm board without a pallet showed a HiP defect cliff, with ~110 µm of board warpage as the practical limit; a pallet eliminated HiP up to ~130 µm.

Countermeasures, in order: lower peak temperature (warpage scales with ΔT from neutral), shorter soak (preserve flux), over-print paste on BGA lands (closes the gap and adds flux), board support/pallet, and specify dynamic warpage to the package supplier — room-temperature coplanarity does not predict HiP, and J-STD-020 coplanarity limits are not a warpage specification. IPC-9641 defines the measurement method (shadow moiré or fringe projection through a simulated reflow profile) but deliberately sets no pass/fail limit; the limit is yours to write into the drawing.

7.3 Voiding in bottom-termination components

A QFN's thermal pad is a 9 mm² plate with a 36–42 µm standoff. Flux volatiles generated under it must escape through that gap, and some do not. The result is voids that raise the thermal resistance of the very path the pad exists to provide.

IPC-7093 does not set a single universal acceptance limit; it discusses the trade-offs and notes that small voids in the thermal pad are not necessarily a reliability problem. The commonly cited ceiling is 50% void area, the working target for most industrial product is 25%, and automotive/high-reliability programmes frequently specify <10%. First-order, thermal resistance scales as:

so 25% voiding costs ~33% of the pad's thermal capability, and 50% doubles it.

What actually reduces voiding: aperture segmentation (a 3×3 or 4×4 grid of smaller squares rather than one 3 mm square, giving volatiles escape paths), 50–70% paste coverage rather than 100%, solder-mask-defined outgassing channels, plugged and capped thermal vias (IPC-4761 Type VII) so paste cannot wick down the barrel, and a paste/flux chemistry with lower volatile content. Reflow profile matters less than aperture design, but a shorter soak and a slower ramp-to-peak both help.

8. Moisture: MSL, popcorning, and the bake rule

Every non-hermetic plastic package absorbs moisture. Heat it above 100 °C fast enough and the vapour pressure delaminates the package, cracks the die, or blows the balls off — "popcorning."

J-STD-020 assigns a moisture sensitivity level; J-STD-033 governs handling. Floor life at ≤30 °C/60% RH:

MSL · Floor life

1 · Unlimited (≤30 °C/85% RH)

2 · 1 year

2a · 4 weeks

3 · 168 hours

4 · 72 hours

5 · 48 hours

5a · 24 hours

6 · Bake before use; reflow within time on label

Most ICs are MSL 3. The trap is not the level, it is the clock: a reel opened on Monday, a build that slips to Thursday, and a 168-hour budget consumed by a humid monsoon week in Chennai. Once floor life is exceeded the part must be baked — 125 °C for 24 h is typical for thick packages, 8–24 h at 125 °C for thin ones, with the exact table in J-STD-033 depending on thickness, MSL and exposure. Parts in tape and reel cannot be baked above 40 °C without damaging the carrier tape, which means a 40 °C bake takes days.

The reflow consequence is direct: absorbed moisture also drives voiding, because the same water that popcorns a BGA is the volatile that cannot escape from under a QFN.

9. Inspection and acceptance

SPI measures every deposit in three dimensions. IPC-7527 provides the framework; a common starting window is 50–150% of target volume with offset ≤25% of pad width, tightened for fine pitch and 0201. Volume alone is a poor control variable — a slowly falling mean volume reveals a clogging aperture long before a single deposit fails, which is why SPI data should be tracked as C_{pk} and trend, not as a pass/fail count. A process running 99% mean volume with 12.8% standard deviation against 50/150 limits is at C_{pk} 1.24 — below the 1.33 usually demanded of a controlled process, even though it produces no rejects.

AOI catches placement, polarity, bridging, and fillet shape on visible joints. It cannot see under a BGA, a QFN, or a shielded module, and its false-call rate is a real cost: an AOI running 2% false calls on 1,000 placements flags 20 good joints per board.

X-ray is the only volumetric check for area-array and bottom-termination joints. Transmission X-ray shows void fraction and shape; 3D CT resolves ball collapse and HiP, which is otherwise invisible — HiP looks like a good joint in 2D because the ball diameter is unchanged.

IPC-A-610 class determines the acceptance criteria. For a Class 3 chip component: minimum end joint width 75% of termination or pad width, minimum fillet height equal to solder thickness plus 25% of termination height (or 0.5 mm, whichever is less), minimum end overlap 25% of termination length, side overhang ≤25%. Class 2 relaxes the fillet height to "evidence of proper wetting." Writing "Class 3" on a purchase order for a consumer product with 0402 passives is a way to pay for scrap you did not need.

Benchmarks. A study covering >1 billion solder joints across 15 companies found average defect levels of 650–1,100 DPMO; high-volume boards run continuously on one line reach 200–600 DPMO. IPC's own benchmark for first-pass yield is >95%, with best-in-class >97%. If a supplier quotes 50 DPMO on a low-volume, high-mix board, ask what they are counting.

10. DFM rules for assembly

These reduce price and reject rate, roughly in order of impact:

  1. Use IPC-7351 density levels deliberately. Level A (most) gives generous pads and easier printing; Level C (least) saves area and costs yield. Pick per footprint, not per board.
  2. Non-solder-mask-defined (NSMD) pads for fine pitch. The mask opening is larger than the copper, so the pad defines the joint and registration tolerance is easier. SMD pads give higher peel strength for large parts but demand tighter mask registration.
  3. Balance copper. A pad on a ground plane next to a pad on a 0.2 mm trace is a tombstone waiting to happen. Thermal reliefs on one side, spokes on the other, or move the plane.
  4. Fiducials: three global, plus local for fine pitch. 1 mm copper dot, 2 mm mask clear, no other copper within 3 mm, not on a panel rail that gets routed away.
  5. Panelize for the line, not for the drawing. 5 mm rails, 3–5 mm between boards, tooling holes on a 2.54 mm grid, mouse bites rather than V-score for anything with components near the edge.
  6. Keep 3 mm clear at board edges for conveyor clamping, and 0.5 mm between components for rework nozzle access.
  7. Fill and cap via-in-pad. IPC-4761 Type VII (filled and covered) or move the via out of the pad. An open via in a thermal pad wicks paste, starves the joint and voids the barrel.
  8. Solder mask web ≥0.1 mm between pads, and 0.05–0.1 mm mask clearance per side. A sliver thinner than the mask's mechanical strength lifts and causes bridging.
  9. Put test points on one side, 1.0 mm minimum, on a 2.54 mm grid. Flying probe needs access; ICT needs a fixture that costs ₹4–15 lakh, which only amortises above ~10,000 units.
  10. Write a complete BOM. MPN, package, tolerance, MSL, and an approved alternate. "10k resistor" without a package is a line item that becomes a purchasing argument.
  11. Do not specify 0402 where 0603 fits. The paste volume, placement accuracy and rework cost all step up; at low volume the difference is larger than the board area saved.
  12. State the acceptance class and the inspection method on the RFQ. Class 2 with AOI and sampling X-ray is a different price from Class 3 with 100% X-ray on every BGA.

11. The cost model

Assembly cost has three terms with completely different scaling:

Published Indian rates for job-work assembly cluster around ₹0.12–0.28 per SMT point (labour and machine only, customer supplies board and components), while full-turnkey quotes land at ₹1–3 per SMD placement and ₹3–5 per through-hole part, with a setup fee of ₹2,000–10,000 per batch. East Asian rapid-prototype shops run $0.001–0.002 per joint, which is why a 100-board run can be cheaper offshore until freight and duty are counted.

Worked example — 100 × 80 mm, 4-layer, ENIG, 120 SMT placements on side A and 30 on side B, quantity 100:

Line item · Basis · Per board

Stencil (laser, framed) · ₹2,500 once · ₹25.00

Programming + setup, 2 sides · ₹6,000 once · ₹60.00

First article + AOI program · ₹2,000 once · ₹20.00

Placement, 150 points · ₹1.20/point · ₹180.00

Reflow, 2 passes · ₹12/pass · ₹24.00

SPI + AOI · per board · ₹20.00

X-ray sampling · per board · ₹5.00

Functional test · per board · ₹30.00

Paste, solder, consumables · per board · ₹12.00

Assembly total · · ₹376.00

At N = 1{,}000 with the same rates: NRE falls to ₹10.50/board and the total to ₹313.50. If the placement rate drops to ₹0.85 at volume, it falls to ₹254. At N = 10: ₹1,322 per board, of which 80% is setup.

The comparison that matters is against hand assembly. 150 joints at ₹3–5 each is ₹450–750 — apparently cheaper at N = 10, except that hand-soldered joints run 2,000–10,000 DPMO, have no fillet consistency, and cannot place a 0.5 mm-pitch QFN at all. The correct comparison is not cost per joint, it is cost per good board plus the cost of the field failure.

The structural point: NRE dominates below ~200 boards, placements dominate above ~2,000, and test dominates when the board has more than one BGA. Optimising placement rate on a 100-piece run is optimising 3% of the price.

12. Choosing a route

What to put on the RFQ so the quotes are comparable: board size and layer count, surface finish (ENIG vs HASL matters for fine pitch and for shelf life), placement count per side, finest pitch and smallest package, BGA/QFN count and pitch, the acceptance class, the inspection method, whether you supply the BOM or they do, MSL handling requirements, and the quantity curve (10/100/1,000). A quote that omits the acceptance class is a quote for a different product.

The numbers to take away

For the bare-board side of this — stackup, impedance, surface finish selection, and the fabrication tolerances that determine whether the pads you designed are the pads you get — see the PCB fabrication guide. The metrology guide covers the measurement systems behind SPI and X-ray, the SPC and capability guide covers how to turn SPI volume data into a controlled process, and the should-cost guide covers the quoting logic that assembly NRE and placement rates feed into.

All profiles, volumes and costs above are computed from the stated assumptions. Paste transfer efficiency, voiding and warpage vary with stencil technology, paste lot, board design and oven; the numbers here are design-stage estimates and should be replaced with measured SPI and thermocouple data before being used to set production limits.

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